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[208.118.235.17]) by mx.google.com with ESMTPS id 66si6277993iom.125.2015.09.09.05.49.53 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 09 Sep 2015 05:49:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:42311 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZeoz-0005pU-DS for patch@linaro.org; Wed, 09 Sep 2015 08:49:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34766) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZaxp-00055f-Ll for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZaxm-00026e-0i for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:45 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:33196) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZaxl-00026P-Pn for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:41 -0400 Received: by pacex6 with SMTP id ex6so4010683pac.0 for ; Wed, 09 Sep 2015 01:42:41 -0700 (PDT) X-Received: by 10.68.218.65 with SMTP id pe1mr67378432pbc.2.1441788161413; Wed, 09 Sep 2015 01:42:41 -0700 (PDT) Received: from localhost.localdomain.amcc.com ([182.73.239.130]) by smtp.gmail.com with ESMTPSA id tz1sm6130244pbc.50.2015.09.09.01.42.36 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Sep 2015 01:42:40 -0700 (PDT) From: Tushar Jagad To: qemu-devel@nongnu.org Date: Wed, 9 Sep 2015 08:42:12 +0000 Message-Id: <1441788132-6286-4-git-send-email-tushar.jagad@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1441788132-6286-1-git-send-email-tushar.jagad@linaro.org> References: <1441788132-6286-1-git-send-email-tushar.jagad@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.51 X-Mailman-Approved-At: Wed, 09 Sep 2015 08:44:56 -0400 Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, patches@apm.com, tushar.jagad@linaro.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH RFC 3/3] arm64: pass breakpoint/watchpoint info for target cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: tushar.jagad@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patch adds support for passing user defined hardware properties to the host kernel for cross cpu environment. ARM cpu has a lot of implementation specific hardware features which differ from vendor to vendor. This pose a hurdle to run guests in a cross cpu type environment (for example: running cortex-a57 guests on x-gene and vice-versa). The implementation specific hardware properties like number of hardware breakpoints, watchpoints, etc needs to be defined for guest for the Cross CPU execution. This is specifically useful in an environment where a mix of hardware platforms are available and the guest cpu needs to be different from the host cpu. Qemu passes this information to the host kernel which reflects these properties accordingly in the guest vcpu. Signed-off-by: Tushar Jagad --- hw/arm/virt.c | 23 ++++++++++++++++++++++- target-arm/cpu-qom.h | 6 ++++++ target-arm/kvm64.c | 8 ++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4846892..23ca35f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -828,6 +828,8 @@ static void machvirt_init(MachineState *machine) ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); CPUClass *cc = CPU_CLASS(oc); Object *cpuobj; + CPUState *cs; + ARMCPU *cpu; Error *err = NULL; char *cpuopts = g_strdup(cpustr[1]); @@ -837,8 +839,11 @@ static void machvirt_init(MachineState *machine) } cpuobj = object_new(object_class_get_name(oc)); + cs = CPU(cpuobj); + cpu = ARM_CPU(cs); + /* Handle any CPU options specified by the user */ - cc->parse_features(CPU(cpuobj), cpuopts, &err); + cc->parse_features(cs, cpuopts, &err); g_free(cpuopts); if (err) { error_report_err(err); @@ -863,6 +868,22 @@ static void machvirt_init(MachineState *machine) } object_property_set_bool(cpuobj, true, "realized", NULL); + + if (object_property_find(cpuobj, "bpts", NULL)) { + cpu->bpts = object_property_get_int(cpuobj, "bpts", &error_abort); + if (cpu->bpts && cpu->bpts < 2) { + printf("Minimum number of breakpoints > 2\n"); + exit(1); + } + } + + if (object_property_find(cpuobj, "wpts", NULL)) { + cpu->wpts = object_property_get_int(cpuobj, "wpts", &error_abort); + if (cpu->wpts && cpu->wpts < 2) { + printf("Minimum number of watchpoints > 2\n"); + exit(1); + } + } } g_strfreev(cpustr); fdt_add_timer_nodes(vbi); diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 3cbc4a0..aceaaab 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -121,6 +121,12 @@ typedef struct ARMCPU { /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; + /* Number of h/w breakpoints supported by the guest */ + uint32_t bpts; + + /* Number of h/w watchpoints supported by the guest */ + uint32_t wpts; + /* Uniprocessor system with MP extensions */ bool mp_is_up; diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index bd60889..39ff54b 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -105,6 +105,14 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; } + if (cpu->bpts) + cpu->kvm_init_features[KVM_ARM_VCPU_BPTS_FEATURES_IDX] |= + (cpu->bpts << KVM_ARM_VCPU_NUM_BPTS) & KVM_ARM_VCPU_BPTS_MASK; + + if (cpu->wpts) + cpu->kvm_init_features[KVM_ARM_VCPU_WPTS_FEATURES_IDX] |= + (cpu->wpts << KVM_ARM_VCPU_NUM_WPTS) & KVM_ARM_VCPU_WPTS_MASK; + /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); if (ret) {