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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id l6si2070265igv.47.2015.09.09.05.54.26 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 09 Sep 2015 05:54:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:42363 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZetN-0004RG-Le for patch@linaro.org; Wed, 09 Sep 2015 08:54:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34710) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZaxj-000555-AZ for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZZaxg-0001vb-4N for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:39 -0400 Received: from mail-pa0-f53.google.com ([209.85.220.53]:33089) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZZaxf-0001v3-WB for qemu-devel@nongnu.org; Wed, 09 Sep 2015 04:42:36 -0400 Received: by pacex6 with SMTP id ex6so4008156pac.0 for ; Wed, 09 Sep 2015 01:42:35 -0700 (PDT) X-Received: by 10.67.15.36 with SMTP id fl4mr57938805pad.152.1441788155532; Wed, 09 Sep 2015 01:42:35 -0700 (PDT) Received: from localhost.localdomain.amcc.com ([182.73.239.130]) by smtp.gmail.com with ESMTPSA id tz1sm6130244pbc.50.2015.09.09.01.42.30 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Sep 2015 01:42:34 -0700 (PDT) From: Tushar Jagad To: qemu-devel@nongnu.org Date: Wed, 9 Sep 2015 08:42:11 +0000 Message-Id: <1441788132-6286-3-git-send-email-tushar.jagad@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1441788132-6286-1-git-send-email-tushar.jagad@linaro.org> References: <1441788132-6286-1-git-send-email-tushar.jagad@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.53 X-Mailman-Approved-At: Wed, 09 Sep 2015 08:44:56 -0400 Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, patches@apm.com, tushar.jagad@linaro.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH RFC 2/3] arm: cross cpu: add new properties for arm cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: tushar.jagad@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 In order to support cross cpu for arm certain properties should be defined by the datacenter admin. This is necessary for migrating guests to different hardware platforms. CPU properties like number of breakpoints, watchpoints and pmu counters are implementation specific. We need to restrict the guest kernel to a specific count considering different mix of hardware platforms in the datacenter. This patch adds new properties for defining hardware in terms of number of breakpoints, watchpoints and pmu counters supported in the guest. Signed-off-by: Tushar Jagad --- target-arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8b4323d..a07613e 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -1349,6 +1349,8 @@ static Property arm_cpu_properties[] = { DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), + DEFINE_PROP_UINT32("bpts", ARMCPU, bpts, 0), + DEFINE_PROP_UINT32("wpts", ARMCPU, wpts, 0), DEFINE_PROP_END_OF_LIST() };