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X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Although we were correctly handling interrupts becoming active and then inactive, we weren't actually exposing this to the guest by setting the 'active' flag for the interrupt, so reads of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly return zeroes. Correct this oversight. Signed-off-by: Peter Maydell Message-id: 1438089748-5528-6-git-send-email-peter.maydell@linaro.org --- hw/intc/arm_gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 9daa8cd..2df550c 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -262,6 +262,7 @@ static void gic_activate_irq(GICState *s, int cpu, int irq) } s->running_priority[cpu] = prio; + GIC_SET_ACTIVE(irq, 1 << cpu); } static int gic_get_prio_from_apr_bits(GICState *s, int cpu) @@ -536,6 +537,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) */ gic_drop_prio(s, cpu, group); + GIC_CLEAR_ACTIVE(irq, cm); gic_update(s); }