From patchwork Fri Sep 4 15:05:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 53119 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f72.google.com (mail-la0-f72.google.com [209.85.215.72]) by patches.linaro.org (Postfix) with ESMTPS id E1DC522E23 for ; Fri, 4 Sep 2015 15:20:21 +0000 (UTC) Received: by laeb10 with SMTP id b10sf8801711lae.1 for ; Fri, 04 Sep 2015 08:20:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=j+n6po/CIRqeGPesj0jTWYYG4LGxuTSGJMZVt18XCpU=; b=Uy6uGE8dwsnSsSnmqlYaTMpX0rsduoeHmJAeDTjGgW17q80TnQ9D07ag85lVsiq3BB aKv816UUTUB2rA+JYCwpbO20RhWo/7MPVF8M7ZIFPnv6zh5THJSk7Kar5aB5XoEb2Wmf rdZrq35SgMRsVQYKNcViu8K1jI2E60OZhHz9qBERdsw+o0kPoiGSG2tVWVyEUaA8yIyX lQ5cR+/8sohdivuxrhk+OtvpJejP7lDJd03A0CdhIUeQJamt7/FvHGPrCq0Ci4T7y6WK R2n6ssmPQnATfFUaoCRnkuJAaOggACjkmyjlKkLmpGlOvv0VrkKstUoBaNgIxtJfC4sC 82cA== X-Gm-Message-State: ALoCoQnU8sl9VNUPOwKGxq7/agItK89JkoR9+GDmZ4uv/AkJ4tjwGLHvzXVNe2J2aKR4nZb6vt6E X-Received: by 10.180.83.226 with SMTP id t2mr1264663wiy.5.1441380020213; Fri, 04 Sep 2015 08:20:20 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.36.135 with SMTP id q7ls314736laj.77.gmail; Fri, 04 Sep 2015 08:20:20 -0700 (PDT) X-Received: by 10.152.7.37 with SMTP id g5mr4205224laa.101.1441380020036; Fri, 04 Sep 2015 08:20:20 -0700 (PDT) Received: from mail-lb0-f169.google.com (mail-lb0-f169.google.com. [209.85.217.169]) by mx.google.com with ESMTPS id yp3si2582686lbb.43.2015.09.04.08.20.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Sep 2015 08:20:19 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) client-ip=209.85.217.169; Received: by lbbmp1 with SMTP id mp1so13225335lbb.1 for ; Fri, 04 Sep 2015 08:20:19 -0700 (PDT) X-Received: by 10.152.21.196 with SMTP id x4mr4119242lae.117.1441380019899; Fri, 04 Sep 2015 08:20:19 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.164.42 with SMTP id yn10csp2054191lbb; Fri, 4 Sep 2015 08:20:19 -0700 (PDT) X-Received: by 10.140.85.8 with SMTP id m8mr6098653qgd.32.1441380018952; Fri, 04 Sep 2015 08:20:18 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k20si3110830qgd.104.2015.09.04.08.20.18 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 04 Sep 2015 08:20:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:60659 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXsmn-00016q-Ji for patch@linaro.org; Fri, 04 Sep 2015 11:20:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38156) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXsZE-0000AY-A1 for qemu-devel@nongnu.org; Fri, 04 Sep 2015 11:06:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZXsZD-0000ta-0R for qemu-devel@nongnu.org; Fri, 04 Sep 2015 11:06:16 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35023) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZXsZC-0000iE-Op for qemu-devel@nongnu.org; Fri, 04 Sep 2015 11:06:14 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZXsYu-0006F2-Es for qemu-devel@nongnu.org; Fri, 04 Sep 2015 16:05:56 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 4 Sep 2015 16:05:36 +0100 Message-Id: <1441379156-23939-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1441379156-23939-1-git-send-email-peter.maydell@linaro.org> References: <1441379156-23939-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 07/27] target-arm/arm-semi.c: Support widening APIs to 64 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The 64-bit A64 semihosting API has some pervasive changes from the 32-bit version: * all parameter blocks are arrays of 64-bit values, not 32-bit * the semihosting call number is passed in W0 * the return value is a 64-bit value in X0 Implement the necessary handling for this widening. Signed-off-by: Peter Maydell Reviewed-by: Christopher Covington Tested-by: Christopher Covington Message-id: 1439483745-28752-7-git-send-email-peter.maydell@linaro.org --- target-arm/arm-semi.c | 69 ++++++++++++++++++++++++++++++++++++++++++--------- target-arm/cpu.h | 2 +- 2 files changed, 58 insertions(+), 13 deletions(-) diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index dbdc211..1d4cc59 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c @@ -134,7 +134,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) #ifdef CONFIG_USER_ONLY TaskState *ts = cs->opaque; #endif - target_ulong reg0 = env->regs[0]; + target_ulong reg0 = is_a64(env) ? env->xregs[0] : env->regs[0]; if (ret == (target_ulong)-1) { #ifdef CONFIG_USER_ONLY @@ -158,7 +158,30 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) break; } } - env->regs[0] = reg0; + if (is_a64(env)) { + env->xregs[0] = reg0; + } else { + env->regs[0] = reg0; + } +} + +static target_ulong arm_flen_buf(ARMCPU *cpu) +{ + /* Return an address in target memory of 64 bytes where the remote + * gdb should write its stat struct. (The format of this structure + * is defined by GDB's remote protocol and is not target-specific.) + * We put this on the guest's stack just below SP. + */ + CPUARMState *env = &cpu->env; + target_ulong sp; + + if (is_a64(env)) { + sp = env->xregs[31]; + } else { + sp = env->regs[13]; + } + + return sp - 64; } static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) @@ -168,8 +191,13 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) /* The size is always stored in big-endian order, extract the value. We assume the size always fit in 32 bits. */ uint32_t size; - cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0); - env->regs[0] = be32_to_cpu(size); + cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0); + size = be32_to_cpu(size); + if (is_a64(env)) { + env->xregs[0] = size; + } else { + env->regs[0] = size; + } #ifdef CONFIG_USER_ONLY ((TaskState *)cs->opaque)->swi_errno = err; #else @@ -193,20 +221,30 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, * the callback function. */ - return env->regs[0]; + return is_a64(env) ? env->xregs[0] : env->regs[0]; } /* Read the input value from the argument block; fail the semihosting * call if the memory read fails. */ #define GET_ARG(n) do { \ - if (get_user_ual(arg ## n, args + (n) * 4)) { \ - return (uint32_t)-1; \ + if (is_a64(env)) { \ + if (get_user_u64(arg ## n, args + (n) * 8)) { \ + return -1; \ + } \ + } else { \ + if (get_user_u32(arg ## n, args + (n) * 4)) { \ + return -1; \ + } \ } \ } while (0) -#define SET_ARG(n, val) put_user_ual(val, args + (n) * 4) -uint32_t do_arm_semihosting(CPUARMState *env) +#define SET_ARG(n, val) \ + (is_a64(env) ? \ + put_user_u64(val, args + (n) * 8) : \ + put_user_u32(val, args + (n) * 4)) + +target_ulong do_arm_semihosting(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); CPUState *cs = CPU(cpu); @@ -222,8 +260,15 @@ uint32_t do_arm_semihosting(CPUARMState *env) CPUARMState *ts = env; #endif - nr = env->regs[0]; - args = env->regs[1]; + if (is_a64(env)) { + /* Note that the syscall number is in W0, not X0 */ + nr = env->xregs[0] & 0xffffffffU; + args = env->xregs[1]; + } else { + nr = env->regs[0]; + args = env->regs[1]; + } + switch (nr) { case TARGET_SYS_OPEN: GET_ARG(0); @@ -355,7 +400,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) GET_ARG(0); if (use_gdb_syscalls()) { return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", - arg0, env->regs[13]-64); + arg0, arm_flen_buf(cpu)); } else { struct stat buf; ret = set_swi_errno(ts, fstat(arg0, &buf)); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 31825d3..0a25335 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -504,7 +504,7 @@ typedef struct CPUARMState { ARMCPU *cpu_arm_init(const char *cpu_model); int cpu_arm_exec(CPUState *cpu); -uint32_t do_arm_semihosting(CPUARMState *env); +target_ulong do_arm_semihosting(CPUARMState *env); void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env);