From patchwork Tue Aug 25 15:00:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 52677 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by patches.linaro.org (Postfix) with ESMTPS id 0405622E8F for ; Tue, 25 Aug 2015 15:01:59 +0000 (UTC) Received: by wilj18 with SMTP id j18sf6883204wil.0 for ; Tue, 25 Aug 2015 08:01:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=Nnll9tnmn2nOgXD0obG4HcvyGVm5a1jtc3wBNxLUb8U=; b=OYNDCxcjxG8FSacACBsCTuCX6M/mb28/WFsVTMgBJoiPnIAOhkfoY+idj0qdL3E/6J lk3ZMxIwMHErHz4ixbADKrjz4FRAtLgwuYDfD9goj7D+liD3Tsqb1xm2NQd9oJkhG1f7 1ug8afh/fw8HC3juXqfWb1n+ZS8RDoaj9LwKBcJjOCUGXTtkyfZeVHr9ueK+QRbFPF5W dyf7lI8dwabNKg8ACWHmJ2uJITsPdB6u/PAf8S6BCZBDec2OmvnvfCVqu4z31Uxan87/ Ag/gE0u5uSFU5ncZGgbUxWyGxlUbnRUkCnYLm75ly/i7xwlUMdqBJvRvR4Y+K3XYK4Ka cKBg== X-Gm-Message-State: ALoCoQmEpDbURHT0qBfK0aEZXW7NJgr4IhkLREHySEkWGT9cCl/SAt4Dn/c86nCOBR4qpnQGqNNX X-Received: by 10.180.35.162 with SMTP id i2mr1023721wij.6.1440514918328; Tue, 25 Aug 2015 08:01:58 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.153.8.171 with SMTP id dl11ls575010lad.28.gmail; Tue, 25 Aug 2015 08:01:58 -0700 (PDT) X-Received: by 10.152.6.231 with SMTP id e7mr26266672laa.78.1440514918127; Tue, 25 Aug 2015 08:01:58 -0700 (PDT) Received: from mail-lb0-f181.google.com (mail-lb0-f181.google.com. [209.85.217.181]) by mx.google.com with ESMTPS id ao8si16228720lbc.40.2015.08.25.08.01.58 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Aug 2015 08:01:58 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) client-ip=209.85.217.181; Received: by lbbtg9 with SMTP id tg9so102057547lbb.1 for ; Tue, 25 Aug 2015 08:01:58 -0700 (PDT) X-Received: by 10.112.235.130 with SMTP id um2mr25844652lbc.72.1440514916925; Tue, 25 Aug 2015 08:01:56 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.162.200 with SMTP id yc8csp3238229lbb; Tue, 25 Aug 2015 08:01:54 -0700 (PDT) X-Received: by 10.140.234.139 with SMTP id f133mr70167824qhc.61.1440514908420; Tue, 25 Aug 2015 08:01:48 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k70si33834535qhc.26.2015.08.25.08.01.47 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 25 Aug 2015 08:01:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:60645 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFjO-0002x4-WD for patch@linaro.org; Tue, 25 Aug 2015 11:01:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35448) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFiA-0001lA-Hm for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUFi9-0001Z8-NH for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:30 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34989) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUFi9-0001NR-HA for qemu-devel@nongnu.org; Tue, 25 Aug 2015 11:00:29 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZUFhx-0004K9-4N for qemu-devel@nongnu.org; Tue, 25 Aug 2015 16:00:17 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 25 Aug 2015 16:00:03 +0100 Message-Id: <1440514816-16562-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> References: <1440514816-16562-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and ACTLR_EL3, for consistency. Since we don't currently have any CPUs that need the EL2/EL3 versions to reset to non-zero values, implement as RAZ/WI. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1438281398-18746-5-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index f6119be..97ca86a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3936,13 +3936,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_AUXCR)) { - ARMCPRegInfo auxcr = { - .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, - .access = PL1_RW, .type = ARM_CP_CONST, - .resetvalue = cpu->reset_auxcr + ARMCPRegInfo auxcr_reginfo[] = { + { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, + .resetvalue = cpu->reset_auxcr }, + { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL3_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + REGINFO_SENTINEL }; - define_one_arm_cp_reg(cpu, &auxcr); + define_arm_cp_regs(cpu, auxcr_reginfo); } if (arm_feature(env, ARM_FEATURE_CBAR)) {