From patchwork Fri Aug 14 10:41:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 52424 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f69.google.com (mail-la0-f69.google.com [209.85.215.69]) by patches.linaro.org (Postfix) with ESMTPS id B428B22B12 for ; Fri, 14 Aug 2015 10:41:36 +0000 (UTC) Received: by lagz9 with SMTP id z9sf26580806lag.3 for ; Fri, 14 Aug 2015 03:41:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=GqUPWB8SSYED0DCPRqRWqUCFt2GAC5RWyIkkH3BffbQ=; b=KxzpTqbzltkyjnLt6aG81Fb37ThkrslqgQ4pAE5RO5oQIcPDlf+wJjOYLEFB9nR3dp 1+ZCDgcFmHh2qN18itEdcFJ4p5/dmlOVordVYiaFJtoyGFWHbLlMxaDIPjmYDV8E8oY5 mXmit5Sx3Y8Y8RYnQaDxLaLkVoK+5dsnpYwcDKDOVStAAPqOkLTvk186SCdugKTB/EwF aAoEQTftRvYbVqK4ebmWGhMoK04EX+wFIa0Zlb01QxVdSzaaFIJksxkIwNKY67CER0SJ wct74ZVHe6NStMa+amYO4iwQaFFD7TyGypfHCLRIRD8PAixrrFtsjwb/M3aduBupiOJK nKXQ== X-Gm-Message-State: ALoCoQl+16gE7JDrJP0PWBYa1J7U24capjTcK4hDDp0437f0yL9sB5yaI+7BwwhbfN/wm1N5UrRy X-Received: by 10.112.99.37 with SMTP id en5mr12749225lbb.7.1439548895700; Fri, 14 Aug 2015 03:41:35 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.42.211 with SMTP id q19ls309698lal.73.gmail; Fri, 14 Aug 2015 03:41:35 -0700 (PDT) X-Received: by 10.152.23.132 with SMTP id m4mr25279122laf.107.1439548895427; Fri, 14 Aug 2015 03:41:35 -0700 (PDT) Received: from mail-la0-f42.google.com (mail-la0-f42.google.com. [209.85.215.42]) by mx.google.com with ESMTPS id ds10si5687095lbc.133.2015.08.14.03.41.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2015 03:41:35 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) client-ip=209.85.215.42; Received: by lagz9 with SMTP id z9so41460740lag.3 for ; Fri, 14 Aug 2015 03:41:35 -0700 (PDT) X-Received: by 10.152.26.163 with SMTP id m3mr42808928lag.86.1439548895224; Fri, 14 Aug 2015 03:41:35 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.7.198 with SMTP id l6csp1518641lba; Fri, 14 Aug 2015 03:41:34 -0700 (PDT) X-Received: by 10.66.161.232 with SMTP id xv8mr55223293pab.137.1439548886628; Fri, 14 Aug 2015 03:41:26 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ke6si8348093pbb.115.2015.08.14.03.41.25 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 14 Aug 2015 03:41:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZQCQJ-0000WX-9x; Fri, 14 Aug 2015 11:41:19 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini Subject: [PATCH v2 4/6] target-arm: Implement missing EL2 TLBI operations Date: Fri, 14 Aug 2015 11:41:17 +0100 Message-Id: <1439548879-1972-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1439548879-1972-1-git-send-email-peter.maydell@linaro.org> References: <1439548879-1972-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Implement the missing TLBI operations that exist only if EL2 is implemented. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/helper.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index aea8b33..77ce718 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2562,6 +2562,16 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *other_cs; + + CPU_FOREACH(other_cs) { + tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); + } +} + static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -3065,10 +3075,22 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, .type = ARM_CP_NO_RAW, .access = PL2_W, .writefn = tlbi_aa64_vae2_write }, + { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_vae2_write }, + { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_alle2is_write }, { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, .type = ARM_CP_NO_RAW, .access = PL2_W, .writefn = tlbi_aa64_vae2is_write }, + { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,