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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id en17si5000853wid.73.2015.08.13.09.51.47 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 13 Aug 2015 09:51:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZPvTl-0007Ue-Ps; Thu, 13 Aug 2015 17:35:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Christopher Covington Subject: [PATCH 7/9] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call Date: Thu, 13 Aug 2015 17:35:43 +0100 Message-Id: <1439483745-28752-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1439483745-28752-1-git-send-email-peter.maydell@linaro.org> References: <1439483745-28752-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The A64 semihosting ABI defines a new call SyncCacheRange for doing a 'clean D-cache and invalidate I-cache' sequence. Since QEMU doesn't implement caches, we can implement this as a nop. Signed-off-by: Peter Maydell Reviewed-by: Christopher Covington --- target-arm/arm-semi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index 1d4cc59..1d0d7aa 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c @@ -58,6 +58,7 @@ #define TARGET_SYS_GET_CMDLINE 0x15 #define TARGET_SYS_HEAPINFO 0x16 #define TARGET_SYS_EXIT 0x18 +#define TARGET_SYS_SYNCCACHE 0x19 /* ADP_Stopped_ApplicationExit is used for exit(0), * anything else is implemented as exit(1) */ @@ -623,6 +624,15 @@ target_ulong do_arm_semihosting(CPUARMState *env) ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; gdb_exit(env, ret); exit(ret); + case TARGET_SYS_SYNCCACHE: + /* Clean the D-cache and invalidate the I-cache for the specified + * virtual address range. This is a nop for us since we don't + * implement caches. This is only present on A64. + */ + if (is_a64(env)) { + return 0; + } + /* fall through -- invalid for A32/T32 */ default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); cpu_dump_state(cs, stderr, fprintf, 0);