From patchwork Thu Aug 13 16:35:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 52396 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f199.google.com (mail-lb0-f199.google.com [209.85.217.199]) by patches.linaro.org (Postfix) with ESMTPS id 1427F22EC6 for ; Thu, 13 Aug 2015 16:35:53 +0000 (UTC) Received: by lbcli1 with SMTP id li1sf18277746lbc.2 for ; Thu, 13 Aug 2015 09:35:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=dp5vS2VNEZzn/qCZY/PEg7y8YSK1xf6Kj9P0ixSZRMU=; b=fT5pg2Y4UW5j8cemXDogOOL1VHCjbIQGaqakwdULFoHgZR6o4FpBk2qPi7z+5kJt2Q 6f/AxhAIMZoK06ZoXC9hsrknygJN4lwAd2of5B3hb5RU/r6YpP8L9TQVlpBtWilTTEX0 XTq2AMkQKJgMmX4YIe5CPweg44Gucm1m/agvzj/Azj0+dQfOZbCYVbeWbJ5KZlzvikBr cxpLQ2iSTFz5ePXcXRYn8OnzVT2jtMXBn8kBLQMkv/ntp/NQpXMh3OSbD5eTk52x/DLj oe9SP49I2H9hZIZm+JTPlv8wJD3rePnj3hfxtjQoKcuWmLY4L6QoTo7FLPQ8ne3/UREu 8Z4g== X-Gm-Message-State: ALoCoQkZV8iIWxNRTsEv+kmg+4VV7AJ33Y4VdJAa6a1AYHezz8e09q+yCCGPUwwCtys8ll2C1SuO X-Received: by 10.112.148.101 with SMTP id tr5mr11418751lbb.13.1439483752133; Thu, 13 Aug 2015 09:35:52 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.8.42 with SMTP id o10ls181295laa.87.gmail; Thu, 13 Aug 2015 09:35:52 -0700 (PDT) X-Received: by 10.152.5.228 with SMTP id v4mr36832485lav.36.1439483751958; Thu, 13 Aug 2015 09:35:51 -0700 (PDT) Received: from mail-lb0-f173.google.com (mail-lb0-f173.google.com. [209.85.217.173]) by mx.google.com with ESMTPS id r11si3082029lby.31.2015.08.13.09.35.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Aug 2015 09:35:51 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) client-ip=209.85.217.173; Received: by lbcbn3 with SMTP id bn3so30123527lbc.2 for ; Thu, 13 Aug 2015 09:35:51 -0700 (PDT) X-Received: by 10.152.28.193 with SMTP id d1mr23402832lah.72.1439483751842; Thu, 13 Aug 2015 09:35:51 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.7.198 with SMTP id l6csp1052616lba; Thu, 13 Aug 2015 09:35:50 -0700 (PDT) X-Received: by 10.55.25.96 with SMTP id k93mr68699636qkh.20.1439483748190; Thu, 13 Aug 2015 09:35:48 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id n7si4555587qge.126.2015.08.13.09.35.47 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 13 Aug 2015 09:35:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZPvTl-0007Um-Sn; Thu, 13 Aug 2015 17:35:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Christopher Covington Subject: [PATCH 9/9] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction Date: Thu, 13 Aug 2015 17:35:45 +0100 Message-Id: <1439483745-28752-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1439483745-28752-1-git-send-email-peter.maydell@linaro.org> References: <1439483745-28752-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , For the A64 instruction set, the semihosting call instruction is 'HLT 0xf000'. Wire this up to call do_arm_semihosting() if semihosting is enabled. Signed-off-by: Peter Maydell Reviewed-by: Christopher Covington --- linux-user/main.c | 3 +++ target-arm/cpu.h | 1 + target-arm/helper-a64.c | 6 ++++++ target-arm/internals.h | 2 ++ target-arm/translate-a64.c | 14 ++++++++++++-- 5 files changed, 24 insertions(+), 2 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index fdee981..56f452e 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1054,6 +1054,9 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, &info); } break; + case EXCP_SEMIHOST: + env->xregs[0] = do_arm_semihosting(env); + break; default: fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e067faa..fd91288 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -56,6 +56,7 @@ #define EXCP_SMC 13 /* Secure Monitor Call */ #define EXCP_VIRQ 14 #define EXCP_VFIQ 15 +#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 08c95a3..02fc9b4 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -514,6 +514,12 @@ void aarch64_cpu_do_interrupt(CPUState *cs) case EXCP_VFIQ: addr += 0x100; break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] = do_arm_semihosting(env); + return; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target-arm/internals.h b/target-arm/internals.h index 924aff9..36a56aa 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -36,6 +36,7 @@ static inline bool excp_is_internal(int excp) || excp == EXCP_HALTED || excp == EXCP_EXCEPTION_EXIT || excp == EXCP_KERNEL_TRAP + || excp == EXCP_SEMIHOST || excp == EXCP_STREX; } @@ -58,6 +59,7 @@ static const char * const excnames[] = { [EXCP_SMC] = "Secure Monitor Call", [EXCP_VIRQ] = "Virtual IRQ", [EXCP_VFIQ] = "Virtual FIQ", + [EXCP_SEMIHOST] = "Semihosting call", }; static inline void arm_log_exception(int idx) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 689f2be..8810760 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -30,6 +30,7 @@ #include "internals.h" #include "qemu/host-utils.h" +#include "exec/semihost.h" #include "exec/gen-icount.h" #include "exec/helper-proto.h" @@ -1553,8 +1554,17 @@ static void disas_exc(DisasContext *s, uint32_t insn) unallocated_encoding(s); break; } - /* HLT */ - unsupported_encoding(s, insn); + /* HLT. This has two purposes. + * Architecturally, it is an external halting debug instruction. + * Since QEMU doesn't implement external debug, we treat this as + * it is required for halting debug disabled: it will UNDEF. + * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. + */ + if (semihosting_enabled() && imm16 == 0xf000) { + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + } else { + unsupported_encoding(s, insn); + } break; case 5: if (op2_ll < 1 || op2_ll > 3) {