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[209.85.212.176]) by mx.google.com with ESMTPS id pr9si9081126wjc.194.2015.07.31.08.57.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 Jul 2015 08:57:03 -0700 (PDT) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 209.85.212.176 as permitted sender) client-ip=209.85.212.176; Received: by wicmv11 with SMTP id mv11so63476739wic.0 for ; Fri, 31 Jul 2015 08:57:03 -0700 (PDT) X-Received: by 10.194.89.5 with SMTP id bk5mr7537141wjb.144.1438358223188; Fri, 31 Jul 2015 08:57:03 -0700 (PDT) Received: from midway01-04-00.lavalab ([81.128.185.50]) by smtp.gmail.com with ESMTPSA id h9sm7810299wjx.20.2015.07.31.08.57.02 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Jul 2015 08:57:02 -0700 (PDT) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, pbonzini@redhat.com Cc: christoffer.dall@linaro.org, patches@linaro.org, p.fedin@samsung.com Subject: [PATCH for-2.5] hw/intc/arm_gic_kvm: set up a flat irqchip routing table Date: Fri, 31 Jul 2015 16:56:45 +0100 Message-Id: <1438358205-7395-1-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.8.3.2 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: eric.auger@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In case the kernel supports GSI routing, we set up irqchip routing entries for GIC SPIs. This is not mandated as long as MSI routing is not used (because the kernel sets a default irqchip routing table). However once MSI routing gets used (for VIRTIO-PCI vhost for example), the first call to KVM_SET_GSI_ROUTING overrides the kernel default irqchip table. If no routing entry exists for the GSI, any IRQFD signaling for this GSI will fail. Signed-off-by: Eric Auger --- gsi routing for ARM is functional but needs to be maturated. The API for MSI routing still is in discussion. See http://www.spinics.net/lists/kvm/msg118792.html --- hw/intc/arm_gic_kvm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index f56bff1..58d8303 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -631,6 +631,18 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, s->dev_fd); + + if (kvm_check_extension(kvm_state, KVM_CAP_IRQ_ROUTING)) { + /* set up irq routing */ + kvm_init_irq_routing(kvm_state); + for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { + kvm_irqchip_add_irq_route(kvm_state, i, 0, i); + } + + kvm_gsi_routing_allowed = true; + + kvm_irqchip_commit_routes(kvm_state); + } } static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)