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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id gs3si20406067wib.29.2015.07.28.06.22.38 for (version=TLS1_2 cipher=AES128-SHA256 bits=128/128); Tue, 28 Jul 2015 06:22:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZK4pw-0001Rw-If; Tue, 28 Jul 2015 14:22:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E. Iglesias" Subject: [PATCH 5/5] hw/intc/arm_gic: Actually set the active bits for active interrupts Date: Tue, 28 Jul 2015 14:22:28 +0100 Message-Id: <1438089748-5528-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1438089748-5528-1-git-send-email-peter.maydell@linaro.org> References: <1438089748-5528-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Although we were correctly handling interrupts becoming active and then inactive, we weren't actually exposing this to the guest by setting the 'active' flag for the interrupt, so reads of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly return zeroes. Correct this oversight. Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 427c221..dc5a44b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -262,6 +262,7 @@ static void gic_activate_irq(GICState *s, int cpu, int irq) } s->running_priority[cpu] = prio; + GIC_SET_ACTIVE(irq, 1 << cpu); } static int gic_get_prio_from_apr_bits(GICState *s, int cpu) @@ -536,6 +537,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) */ gic_drop_prio(s, cpu, group); + GIC_CLEAR_ACTIVE(irq, cm); gic_update(s); }