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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id du5si53119872pdb.92.2015.07.28.06.22.33 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 28 Jul 2015 06:22:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZK4pw-0001Rk-E7; Tue, 28 Jul 2015 14:22:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E. Iglesias" Subject: [PATCH 2/5] hw/intc/arm_gic: Running priority is group priority, not full priority Date: Tue, 28 Jul 2015 14:22:25 +0100 Message-Id: <1438089748-5528-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1438089748-5528-1-git-send-email-peter.maydell@linaro.org> References: <1438089748-5528-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Priority values for the GIC are divided into a "group priority" and a "subpriority" (with the division being determined by the binary point register). The running priority is only determined by the group priority of the active interrupts, not the subpriority. In particular, this means that there can't be more than one active interrupt at any particular group priority. Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 454bfd7..9814bb9 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -219,13 +219,39 @@ static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, return pending_irq; } +static int gic_get_group_priority(GICState *s, int cpu, int irq) +{ + /* Return the group priority of the specified interrupt + * (which is the top bits of its priority, with the number + * of bits masked determined by the applicable binary point register). + */ + int bpr; + uint32_t mask; + + if (gic_has_groups(s) && + !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && + GIC_TEST_GROUP(irq, (1 << cpu))) { + bpr = s->abpr[cpu]; + } else { + bpr = s->bpr[cpu]; + } + + /* a BPR of 0 means the group priority bits are [7:1]; + * a BPR of 1 means they are [7:2], and so on down to + * a BPR of 7 meaning no group priority bits at all. + */ + mask = ~0U << ((bpr & 7) + 1); + + return GIC_GET_PRIORITY(irq, cpu) & mask; +} + static void gic_set_running_irq(GICState *s, int cpu, int irq) { s->running_irq[cpu] = irq; if (irq == 1023) { s->running_priority[cpu] = 0x100; } else { - s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); + s->running_priority[cpu] = gic_get_group_priority(s, cpu, irq); } gic_update(s); }