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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id gm10si13678667wib.91.2015.07.13.07.24.26 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 13 Jul 2015 07:24:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZEeef-0005Pf-Dm; Mon, 13 Jul 2015 15:24:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, davidcdueck@googlemail.com, "Edgar E. Iglesias" Subject: [PATCH for-2.4] target-arm: Fix broken SCTLR_EL3 reset Date: Mon, 13 Jul 2015 15:24:25 +0100 Message-Id: <1436797465-20782-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The SCTLR_EL3 cpreg definition was implicitly resetting the register state to 0, which is both wrong and clashes with the reset done via the SCTLR definition (since sctlr[3] is unioned with sctlr_s). This went unnoticed until recently, when an unrelated change (commit a903c449b41f105aa) happened to perturb the order of enumeration through the cpregs hashtable for reset such that the erroneous reset happened after the correct one rather than before it. Fix this by marking SCTLR_EL3 as an alias, so its reset is left up to the AArch32 view. Signed-off-by: Peter Maydell --- This was causing Greg's trustzone testsuite to fail. target-arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index b87afe7..01f0d0d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2752,6 +2752,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write, .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },