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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id qa7si38108308lbc.18.2015.06.30.06.07.32 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 30 Jun 2015 06:07:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z9vG5-0000nc-Us; Tue, 30 Jun 2015 14:07:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Peter Crosthwaite , "Edgar E. Iglesias" , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 3/5] hw/arm/boot: Configure secure GIC to make IRQs NS if booting an NS kernel Date: Tue, 30 Jun 2015 14:07:27 +0100 Message-Id: <1435669649-3035-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1435669649-3035-1-git-send-email-peter.maydell@linaro.org> References: <1435669649-3035-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.54 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , If our builtin kernel bootloader is directly booting a kernel in the NonSecure world, then we must configure the GIC to put all the IRQs into the NonSecure group. (By default all interrupts are configured to be Secure on reset, which means that a NonSecure guest kernel cannot use any of them.) This job would usually be done by the Secure boot firmware, but our builtin bootloader is doing the job of firmware. Signed-off-by: Peter Maydell --- hw/arm/boot.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 1e7fd28..3974499 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -13,6 +13,7 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" +#include "hw/intc/arm_gic_common.h" #include "elf.h" #include "sysemu/device_tree.h" #include "qemu/config-file.h" @@ -557,6 +558,33 @@ static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, fw_cfg_add_bytes(fw_cfg, data_key, data, size); } +static int find_gics(Object *obj, void *opaque) +{ + GICState *gic = (GICState *)object_dynamic_cast(obj, TYPE_ARM_GIC_COMMON); + bool has_sec_extns; + + if (!gic) { + /* Might be a container, traverse it for children */ + return object_child_foreach(obj, find_gics, opaque); + } + + has_sec_extns = object_property_get_bool(obj, "has-security-extensions", + &error_abort); + if (has_sec_extns) { + object_property_set_bool(obj, true, "irqs-reset-nonsecure", + &error_abort); + } + return 0; +} + +static void reconfigure_gics_nonsecure(void) +{ + /* Find every GIC in the system and tell it to reconfigure + * itself with interrupts as NonSecure. + */ + object_child_foreach(qdev_get_machine(), find_gics, NULL); +} + static void arm_load_kernel_notify(Notifier *notifier, void *data) { CPUState *cs; @@ -767,6 +795,17 @@ static void arm_load_kernel_notify(Notifier *notifier, void *data) } info->is_linux = is_linux; + if (is_linux && arm_feature(&cpu->env, ARM_FEATURE_EL3) && + !info->secure_boot) { + /* We're directly booting a kernel into NonSecure. If the system + * has a GIC which implements the security extensions then we must + * configure it to have all the interrupts be NonSecure (this is + * a job that is done by the Secure boot firmware, and boot.c is + * a minimalist firmware-and-boot-loader equivalent). + */ + reconfigure_gics_nonsecure(); + } + for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) { ARM_CPU(cs)->env.boot_info = info; }