From patchwork Mon Jun 29 18:25:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 50440 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f72.google.com (mail-wg0-f72.google.com [74.125.82.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id CFBF9218E4 for ; Mon, 29 Jun 2015 18:25:49 +0000 (UTC) Received: by wguu7 with SMTP id u7sf49836091wgu.0 for ; Mon, 29 Jun 2015 11:25:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=StCu5pk0+TB9u0FMKAylpPJacp0bWl8pbO0VU9+PqFU=; b=LFJuAf18fjWxJyZs+nbdzrnh+quLVXlgNjvL0F5joHpLxn5YOHxMfdKbtkFtB5caTH zHmtz389YbinQ2bulgHMt8Vckg16robzU0QFWG1/E2TRMf6WsZAh4of2hYu9u7L2gTnW LXN/N3qXGytgnQPj+UDmyZ1AzyDLhIrycUMbpCiW0QeyeEYCjbV/KbP7iAY5CIxh8mJD kUfxIDwHRbgh6vYekmMHdY2jFPjBDPxY5Y3ZN2dOlEqEXtL8bKH27VikZwnnf4CZoV4E ypbrYjneJ4D12+gHWCYU7sXvH/LSYrfq6E9T+jts5cRI93EViu7aePVjf77c1yjFD95D /6lQ== X-Gm-Message-State: ALoCoQkhwsmoUauOpjQXjN/uW4fClT2JOOSp78JKVqluxAxx1nKb5xJuNi6buhMRZImcekxaEarg X-Received: by 10.152.120.69 with SMTP id la5mr10953988lab.7.1435602349123; Mon, 29 Jun 2015 11:25:49 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.20.10 with SMTP id j10ls476244lae.6.gmail; Mon, 29 Jun 2015 11:25:48 -0700 (PDT) X-Received: by 10.112.137.164 with SMTP id qj4mr15370293lbb.105.1435602348848; Mon, 29 Jun 2015 11:25:48 -0700 (PDT) Received: from mail-la0-f53.google.com (mail-la0-f53.google.com. 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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id fq10si14513057wib.108.2015.06.29.11.25.47 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 29 Jun 2015 11:25:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z9dkX-0008Nz-BU; Mon, 29 Jun 2015 19:25:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Peter Crosthwaite , "Edgar E. Iglesias" Subject: [PATCH for-2.4] hw/intc/arm_gic_common.c: Reset all registers Date: Mon, 29 Jun 2015 19:25:45 +0100 Message-Id: <1435602345-32210-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The arm_gic_common reset function was missing reset code for several of the GIC's state fields: * bpr[] * abpr[] * priority1[] * priority2[] * sgi_pending[] * irq_target[] (SMP configurations only) These probably went unnoticed because most guests will either never touch them, or will write to them in the process of configuring the GIC before enabling interrupts. Signed-off-by: Peter Maydell --- The reason for using loops to set these array elements to 0 rather than using memset() is that to support "directly boot a kernel in NS on a TZ-aware GIC and CPU" we need to support resetting the priority registers (most notably the CPU priority mask) to 0x80 rather than 0. I found this via code review rather than because it triggered any kind of misbehaviour. last_active[] does not need any reset, I believe. hw/intc/arm_gic_common.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 044ad66..a64d071 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -123,7 +123,7 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp) static void arm_gic_common_reset(DeviceState *dev) { GICState *s = ARM_GIC_COMMON(dev); - int i; + int i, j; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { if (s->revision == REV_11MPCORE) { @@ -135,15 +135,30 @@ static void arm_gic_common_reset(DeviceState *dev) s->running_irq[i] = 1023; s->running_priority[i] = 0x100; s->cpu_ctlr[i] = 0; + s->bpr[i] = GIC_MIN_BPR; + s->abpr[i] = GIC_MIN_ABPR; + for (j = 0; j < GIC_INTERNAL; j++) { + s->priority1[j][i] = 0; + } + for (j = 0; j < GIC_NR_SGIS; j++) { + s->sgi_pending[j][i] = 0; + } } for (i = 0; i < GIC_NR_SGIS; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_EDGE_TRIGGER(i); } - if (s->num_cpu == 1) { + + for (i = 0; i < ARRAY_SIZE(s->priority2); i++) { + s->priority2[i] = 0; + } + + for (i = 0; i < GIC_MAXIRQ; i++) { /* For uniprocessor GICs all interrupts always target the sole CPU */ - for (i = 0; i < GIC_MAXIRQ; i++) { + if (s->num_cpu == 1) { s->irq_target[i] = 1; + } else { + s->irq_target[i] = 0; } } s->ctlr = 0;