From patchwork Fri Jun 19 13:47:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 50107 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f200.google.com (mail-wi0-f200.google.com [209.85.212.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 230B822903 for ; Fri, 19 Jun 2015 13:50:25 +0000 (UTC) Received: by wizw5 with SMTP id w5sf5490427wiz.2 for ; Fri, 19 Jun 2015 06:50:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=ikjRkeRsCFf0yH9dtwRelIuJAj68Rak8p0UaBNKnUQ0=; b=ed9Q6hYn22aB5WCNK6+5slTGeH837KKCBJKXYy8n2tYc/T4JAFAHuIBWE3/5tWufmK iJ04Zak0HDvmbVYrl1yIYSss09agGaty2I43Zfs6pROxX+pscu6u1AxLjWcmk5gU8NwD Lkdc+Dr+1fVwH6ft4YoiLCYks+whk1YyozD5gepM7XUX/BP0tzT75HGSGJRxcs8+07K9 x2QbmoCERI/TDlrlgPBJfhF8xNHyg8xOI5WrAYzgWZ+FLAc/ScRgVDoEQlCwmQFUqN3o EdC/YmogqNlPLVCy4oFxDS3GssFTH0BtSBVCW85Mg7p4e1Qfs0jFUNGZUAwXRdZvwWey MS/w== X-Gm-Message-State: ALoCoQm+m72aZK0NqxQkyqQdUtiMnSRxvoTDdI3v3ztoUOZS6lrh7LZlCLyUYxxU6crKbXJo3FS/ X-Received: by 10.152.42.208 with SMTP id q16mr15238644lal.9.1434721824356; Fri, 19 Jun 2015 06:50:24 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.178.195 with SMTP id da3ls620000lac.43.gmail; Fri, 19 Jun 2015 06:50:24 -0700 (PDT) X-Received: by 10.112.126.101 with SMTP id mx5mr12786352lbb.35.1434721824125; Fri, 19 Jun 2015 06:50:24 -0700 (PDT) Received: from mail-la0-f42.google.com (mail-la0-f42.google.com. [209.85.215.42]) by mx.google.com with ESMTPS id ap4si6696826lac.21.2015.06.19.06.50.24 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jun 2015 06:50:24 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) client-ip=209.85.215.42; Received: by laka10 with SMTP id a10so74612296lak.0 for ; Fri, 19 Jun 2015 06:50:24 -0700 (PDT) X-Received: by 10.152.206.75 with SMTP id lm11mr17575485lac.41.1434721823974; Fri, 19 Jun 2015 06:50:23 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp607906lbb; Fri, 19 Jun 2015 06:50:23 -0700 (PDT) X-Received: by 10.55.19.140 with SMTP id 12mr35726005qkt.64.1434721821134; Fri, 19 Jun 2015 06:50:21 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b132si10921942qka.45.2015.06.19.06.50.20 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 19 Jun 2015 06:50:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:58173 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wgW-0003Ro-B5 for patch@linaro.org; Fri, 19 Jun 2015 09:50:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35742) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wdd-0006Gw-BC for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:47:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5wdb-0001JD-Rc for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:47:21 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wdb-0001Hr-IS for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:47:19 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z5wdY-0006c5-SJ for qemu-devel@nongnu.org; Fri, 19 Jun 2015 14:47:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 19 Jun 2015 14:47:12 +0100 Message-Id: <1434721636-25357-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1434721636-25357-1-git-send-email-peter.maydell@linaro.org> References: <1434721636-25357-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 08/12] arm: xlnx-zynqmp: Preface CPU variables with "apu" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Peter Crosthwaite The CPUs currently supported by zynqmp are the APU (application processing unit) CPUs. There are other CPUs in Zynqmp so unqualified "cpus" in ambiguous. Preface the variables with "APU" accordingly, to prepare support adding the RPU (realtime processing unit) processors. Signed-off-by: Peter Crosthwaite Reviewed-by: Edgar E. Iglesias Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++------------ include/hw/arm/xlnx-zynqmp.h | 4 ++-- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c index b924f5e..7a98dd6 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-ep108.c @@ -65,7 +65,7 @@ static void xlnx_ep108_init(MachineState *machine) xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline; xlnx_ep108_binfo.initrd_filename = machine->initrd_filename; xlnx_ep108_binfo.loader_start = 0; - arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo); + arm_load_kernel(&s->soc.apu_cpu[0], &xlnx_ep108_binfo); } static QEMUMachine xlnx_ep108_machine = { diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 6b01965..353ecad 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -64,10 +64,10 @@ static void xlnx_zynqmp_init(Object *obj) XlnxZynqMPState *s = XLNX_ZYNQMP(obj); int i; - for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { - object_initialize(&s->cpu[i], sizeof(s->cpu[i]), + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), "cortex-a53-" TYPE_ARM_CPU); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), + object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), &error_abort); } @@ -95,7 +95,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); - qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err) { error_propagate((errp), (err)); @@ -121,38 +121,40 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } } - for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { qemu_irq irq; - object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, + object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, "psci-conduit", &error_abort); if (i > 0) { /* Secondary CPUs start in PSCI powered-down state */ - object_property_set_bool(OBJECT(&s->cpu[i]), true, + object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "start-powered-off", &error_abort); } - object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR, + object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, "reset-cbar", &err); if (err) { error_propagate((errp), (err)); return; } - object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); + object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", + &err); if (err) { error_propagate((errp), (err)); return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_IRQ)); irq = qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); irq = qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); } for (i = 0; i < GIC_NUM_SPI_INTR; i++) { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 79c2b0b..d042df1 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -27,7 +27,7 @@ #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ TYPE_XLNX_ZYNQMP) -#define XLNX_ZYNQMP_NUM_CPUS 4 +#define XLNX_ZYNQMP_NUM_APU_CPUS 4 #define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_NUM_UARTS 2 @@ -47,7 +47,7 @@ typedef struct XlnxZynqMPState { DeviceState parent_obj; /*< public >*/ - ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS]; + ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];