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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id wc1si11821197wjc.45.2015.06.09.07.50.41 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 09 Jun 2015 07:50:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z2KrQ-0007qU-Tq; Tue, 09 Jun 2015 15:50:40 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Robert Buhren Subject: [PATCH] target-arm: Correct "preferred return address" for cpreg access exceptions Date: Tue, 9 Jun 2015 15:50:40 +0100 Message-Id: <1433861440-30133-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The architecture defines that when taking an exception trying to access a coprocessor register, the "preferred return address" for the exception is the address of the instruction that caused the exception. Correct an off-by-4 error which meant we were returning the address after the instruction for traps which happened because of a failure of a runtime access-check function on an AArch32 register. (Traps caused by translate-time checkable permissions failures had the correct address, as did traps on AArch64 registers.) This fixes https://bugs.launchpad.net/qemu/+bug/1463338 Reported-by: Robert Buhren Signed-off-by: Peter Maydell --- target-arm/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 39692d7..239322d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7175,7 +7175,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) break; } - gen_set_pc_im(s, s->pc); + gen_set_pc_im(s, s->pc - 4); tmpptr = tcg_const_ptr(ri); tcg_syn = tcg_const_i32(syndrome); gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn);