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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w134si14360737qha.90.2015.06.01.18.11.53 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 01 Jun 2015 18:11:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:55339 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzakC-0003DN-Eb for patch@linaro.org; Mon, 01 Jun 2015 21:11:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzajT-0002P8-MO for qemu-devel@nongnu.org; Mon, 01 Jun 2015 21:11:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzajQ-0008OT-AD for qemu-devel@nongnu.org; Mon, 01 Jun 2015 21:11:07 -0400 Received: from mail-ob0-f174.google.com ([209.85.214.174]:35330) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzajQ-0008OB-5V for qemu-devel@nongnu.org; Mon, 01 Jun 2015 21:11:04 -0400 Received: by obcnx10 with SMTP id nx10so111370645obc.2 for ; Mon, 01 Jun 2015 18:11:03 -0700 (PDT) X-Received: by 10.202.104.223 with SMTP id o92mr19369253oik.19.1433207463855; Mon, 01 Jun 2015 18:11:03 -0700 (PDT) Received: from localhost ([167.160.116.34]) by mx.google.com with ESMTPSA id t6sm8488094oek.14.2015.06.01.18.11.01 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 01 Jun 2015 18:11:03 -0700 (PDT) From: shannon.zhao@linaro.org To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 2 Jun 2015 09:10:51 +0800 Message-Id: <1433207452-4512-2-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1433207452-4512-1-git-send-email-shannon.zhao@linaro.org> References: <1433207452-4512-1-git-send-email-shannon.zhao@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.174 Cc: shannon.zhao@linaro.org, zhaoshenglong@huawei.com Subject: [Qemu-devel] [PATCH v2 1/2] target-arm/kvm64: Add cortex-a53 cpu support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has added Cortex-A53 cpu support for target-arm, this patch just enables it for kvm-arm. Here adding XGENE_POTENZA just makes the enum continuous. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao --- target-arm/cpu64.c | 1 + target-arm/kvm-consts.h | 4 ++++ target-arm/kvm64.c | 2 ++ 3 files changed, 7 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bf7dd68..dd6f9d8 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -159,6 +159,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; cpu->midr = 0x410fd034; cpu->reset_fpsid = 0x41034070; cpu->mvfr0 = 0x10110222; diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h index aea12f1..943bf89 100644 --- a/target-arm/kvm-consts.h +++ b/target-arm/kvm-consts.h @@ -127,6 +127,8 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) #define QEMU_KVM_ARM_TARGET_AEM_V8 0 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 +#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3 +#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 /* There's no kernel define for this: sentinel value which * matches no KVM target value for either 64 or 32 bit @@ -137,6 +139,8 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53) #else MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 93c1ca8..cd84132 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -50,6 +50,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_CORTEX_A57, + KVM_ARM_TARGET_XGENE_POTENZA, + KVM_ARM_TARGET_CORTEX_A53, QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init;