From patchwork Fri May 29 13:10:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 49206 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f198.google.com (mail-lb0-f198.google.com [209.85.217.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D0798218E7 for ; Fri, 29 May 2015 13:27:09 +0000 (UTC) Received: by lbcue7 with SMTP id ue7sf19066055lbc.3 for ; Fri, 29 May 2015 06:27:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=V9NtqxIIFeR6Q9/qp6wjEx8EdGyZT+M9Q1ioImf+JzM=; b=PsKsjBoO/wbhowsXT5GT6kxO/FLG1UjwDpveKXibM+aOz5wVNmW38bj/t3a9FA6E1l kLM3FeF/pQyTwR892moSdsoMfESzgwTbme8igSpRDkRxldjBi3gMXfZxuxX3Q5ltvaz3 fc+xb8/0qvAO5rXlc/AgLdV2JNyKtc7G4HbJf9tmir38brt3ZyVZnHgTtuMov3A2JTCO Pnf1Q0q+PiWg97pGoRaB1M7muLOvPtY3LZe/fOF4LgXpZyafjBGNtlfbrS3aLo1HyjNX M4khgTpp+MGPUzWn5f1Iyf5+VMCnfWkR6a9GfDbhozkzw10MbQsEWqbKBPRKiOTyRoyj 1k7w== X-Gm-Message-State: ALoCoQkStkC+0n7WYpA+DGnH4g0XTllLbPP2AUAm3OnMaR6pxRVSvC7yL2DZncntSKX5Ss7IowT5 X-Received: by 10.152.22.71 with SMTP id b7mr6168793laf.3.1432906028733; Fri, 29 May 2015 06:27:08 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.225.134 with SMTP id rk6ls343119lac.83.gmail; Fri, 29 May 2015 06:27:08 -0700 (PDT) X-Received: by 10.112.156.231 with SMTP id wh7mr4083311lbb.118.1432906028533; Fri, 29 May 2015 06:27:08 -0700 (PDT) Received: from mail-la0-f49.google.com (mail-la0-f49.google.com. [209.85.215.49]) by mx.google.com with ESMTPS id rt1si4683107lbb.121.2015.05.29.06.27.08 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 May 2015 06:27:08 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) client-ip=209.85.215.49; Received: by laat2 with SMTP id t2so55711573laa.1 for ; Fri, 29 May 2015 06:27:08 -0700 (PDT) X-Received: by 10.112.155.197 with SMTP id vy5mr7851116lbb.29.1432906028253; Fri, 29 May 2015 06:27:08 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp332986lbb; Fri, 29 May 2015 06:27:07 -0700 (PDT) X-Received: by 10.55.18.155 with SMTP id 27mr15987252qks.36.1432906026769; Fri, 29 May 2015 06:27:06 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id e30si5554018qkh.102.2015.05.29.06.27.06 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 29 May 2015 06:27:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:35901 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyKJV-0000Us-RC for patch@linaro.org; Fri, 29 May 2015 09:27:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyK40-0003xc-5p for qemu-devel@nongnu.org; Fri, 29 May 2015 09:11:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyK3x-0003bS-Ba for qemu-devel@nongnu.org; Fri, 29 May 2015 09:11:03 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyK3x-0003US-5A for qemu-devel@nongnu.org; Fri, 29 May 2015 09:11:01 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YyK3h-0005mU-PR for qemu-devel@nongnu.org; Fri, 29 May 2015 14:10:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 29 May 2015 14:10:18 +0100 Message-Id: <1432905045-22138-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1432905045-22138-1-git-send-email-peter.maydell@linaro.org> References: <1432905045-22138-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 12/39] target-arm: Move TB flags down to fill gap X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index bf37c49..21b5b8e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState *env) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime */ -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 +#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) /* Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -#define ARM_TBFLAG_NS_SHIFT 22 +#define ARM_TBFLAG_NS_SHIFT 19 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) /* Bit usage when in AArch64 state: currently we have no A64 specific bits */