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[208.118.235.17]) by mx.google.com with ESMTPS id z9si2179391qcn.27.2015.05.28.05.19.06 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 28 May 2015 05:19:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:58374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxwmA-00085Q-DE for patch@linaro.org; Thu, 28 May 2015 08:19:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58076) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yxwe4-0002DO-8d for qemu-devel@nongnu.org; Thu, 28 May 2015 08:10:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yxwe0-0003WM-Bs for qemu-devel@nongnu.org; Thu, 28 May 2015 08:10:44 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:45228) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yxwdx-0003Qt-Su; Thu, 28 May 2015 08:10:40 -0400 Received: from 172.24.2.119 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id COP98087; Thu, 28 May 2015 20:10:28 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.158.1; Thu, 28 May 2015 20:09:56 +0800 From: Shannon Zhao To: Date: Thu, 28 May 2015 20:08:28 +0800 Message-ID: <1432814932-12608-6-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1432814932-12608-1-git-send-email-zhaoshenglong@huawei.com> References: <1432814932-12608-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 58.251.152.64 Cc: qemu-trivial@nongnu.org, pbonzini@redhat.com, mjt@tls.msk.ru, shannon.zhao@linaro.org, peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH 05/29] hw/isa/lpc_ich9.c: Fix memory leak spotted by valgrind X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao valgrind complains about: ==25058== 8 bytes in 1 blocks are definitely lost in loss record 623 of 3,473 ==25058== at 0x4C2845D: malloc (in /usr/lib64/valgrind/vgpreload_memcheck-amd64-linux.so) ==25058== by 0x2EB657: malloc_and_trace (vl.c:2556) ==25058== by 0x64C770E: g_malloc (in /usr/lib64/libglib-2.0.so.0.3600.3) ==25058== by 0x377C27: qemu_extend_irqs (irq.c:55) ==25058== by 0x377CB3: qemu_allocate_irqs (irq.c:64) ==25058== by 0x222338: ich9_lpc_pm_init (lpc_ich9.c:365) ==25058== by 0x255C42: pc_q35_init (pc_q35.c:255) ==25058== by 0x2EFA22: main (vl.c:4249) Since ich9_lpc_pm_init only requests one irq, so let it just call qemu_allocate_irq. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao --- hw/isa/lpc_ich9.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index dba7585..144b210 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -360,11 +360,8 @@ static void ich9_set_sci(void *opaque, int irq_num, int level) void ich9_lpc_pm_init(PCIDevice *lpc_pci) { ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); - qemu_irq *sci_irq; - - sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1); - ich9_pm_init(lpc_pci, &lpc->pm, sci_irq[0]); + ich9_pm_init(lpc_pci, &lpc->pm, qemu_allocate_irq(ich9_set_sci, lpc, 0)); ich9_lpc_reset(&lpc->d.qdev); }