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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id s7si3139429qck.47.2015.05.24.20.03.01 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 24 May 2015 20:03:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:41672 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwifN-0006gw-GG for patch@linaro.org; Sun, 24 May 2015 23:03:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47898) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwiZE-0003Iw-Iu for qemu-devel@nongnu.org; Sun, 24 May 2015 22:56:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YwiZ7-0000fw-H8 for qemu-devel@nongnu.org; Sun, 24 May 2015 22:56:40 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:61656) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwiZ6-0000fC-FN for qemu-devel@nongnu.org; Sun, 24 May 2015 22:56:33 -0400 Received: from 172.24.2.119 (EHLO szxeml428-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CLV56085; Mon, 25 May 2015 10:56:10 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.158.1; Mon, 25 May 2015 10:56:00 +0800 From: Shannon Zhao To: , , , , , , , , , , Date: Mon, 25 May 2015 10:54:57 +0800 Message-ID: <1432522520-8068-2-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1432522520-8068-1-git-send-email-zhaoshenglong@huawei.com> References: <1432522520-8068-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.65 Cc: hangaohuai@huawei.com, zhaoshenglong@huawei.com, peter.huangpeng@huawei.com, shannon.zhao@linaro.org Subject: [Qemu-devel] [PATCH v9 01/24] hw/acpi/aml-build: Make enum values to be upper case to match coding style X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Igor Mammedov --- hw/acpi/aml-build.c | 12 ++++---- hw/i386/acpi-build.c | 58 +++++++++++++++++++------------------- include/hw/acpi/aml-build.h | 68 ++++++++++++++++++++++----------------------- 3 files changed, 69 insertions(+), 69 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 77ce00b..7a478ae 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -833,7 +833,7 @@ Aml *aml_word_bus_number(AmlMinFixed min_fixed, AmlMaxFixed max_fixed, uint16_t addr_trans, uint16_t len) { - return aml_word_as_desc(aml_bus_number_range, min_fixed, max_fixed, dec, + return aml_word_as_desc(AML_BUS_NUMBER_RANGE, min_fixed, max_fixed, dec, addr_gran, addr_min, addr_max, addr_trans, len, 0); } @@ -850,7 +850,7 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed, uint16_t len) { - return aml_word_as_desc(aml_io_range, min_fixed, max_fixed, dec, + return aml_word_as_desc(AML_IO_RANGE, min_fixed, max_fixed, dec, addr_gran, addr_min, addr_max, addr_trans, len, isa_ranges); } @@ -862,7 +862,7 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed, * ACPI 5.0: 19.5.34 DWordMemory (DWord Memory Resource Descriptor Macro) */ Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed, - AmlMaxFixed max_fixed, AmlCacheble cacheable, + AmlMaxFixed max_fixed, AmlCacheable cacheable, AmlReadAndWrite read_and_write, uint32_t addr_gran, uint32_t addr_min, uint32_t addr_max, uint32_t addr_trans, @@ -870,7 +870,7 @@ Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed, { uint8_t flags = read_and_write | (cacheable << 1); - return aml_dword_as_desc(aml_memory_range, min_fixed, max_fixed, + return aml_dword_as_desc(AML_MEMORY_RANGE, min_fixed, max_fixed, dec, addr_gran, addr_min, addr_max, addr_trans, len, flags); } @@ -882,7 +882,7 @@ Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed, * ACPI 5.0: 19.5.102 QWordMemory (QWord Memory Resource Descriptor Macro) */ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed, - AmlMaxFixed max_fixed, AmlCacheble cacheable, + AmlMaxFixed max_fixed, AmlCacheable cacheable, AmlReadAndWrite read_and_write, uint64_t addr_gran, uint64_t addr_min, uint64_t addr_max, uint64_t addr_trans, @@ -890,7 +890,7 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed, { uint8_t flags = read_and_write | (cacheable << 1); - return aml_qword_as_desc(aml_memory_range, min_fixed, max_fixed, + return aml_qword_as_desc(AML_MEMORY_RANGE, min_fixed, max_fixed, dec, addr_gran, addr_min, addr_max, addr_trans, len, flags); } diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 73259e7..c7c6b61 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -620,31 +620,31 @@ build_ssdt(GArray *table_data, GArray *linker, /* build PCI0._CRS */ crs = aml_resource_template(); aml_append(crs, - aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); - aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); + aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); aml_append(crs, - aml_word_io(aml_min_fixed, aml_max_fixed, - aml_pos_decode, aml_entire_range, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); aml_append(crs, - aml_word_io(aml_min_fixed, aml_max_fixed, - aml_pos_decode, aml_entire_range, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); aml_append(crs, - aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, - aml_cacheable, aml_ReadWrite, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); aml_append(crs, - aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, - aml_non_cacheable, aml_ReadWrite, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0, pci->w32.begin, pci->w32.end - 1, 0, pci->w32.end - pci->w32.begin)); if (pci->w64.begin) { aml_append(crs, - aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, - aml_cacheable, aml_ReadWrite, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, 0, pci->w64.begin, pci->w64.end - 1, 0, pci->w64.end - pci->w64.begin)); } @@ -658,7 +658,7 @@ build_ssdt(GArray *table_data, GArray *linker, aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); crs = aml_resource_template(); aml_append(crs, - aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) + aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len) ); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); @@ -673,7 +673,7 @@ build_ssdt(GArray *table_data, GArray *linker, aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); crs = aml_resource_template(); aml_append(crs, - aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1, + aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, pm->pcihp_io_len) ); aml_append(dev, aml_name_decl("_CRS", crs)); @@ -720,7 +720,7 @@ build_ssdt(GArray *table_data, GArray *linker, crs = aml_resource_template(); aml_append(crs, - aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base, + aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 0x01, APPLESMC_MAX_DATA_LENGTH) ); aml_append(crs, aml_irq_no_flags(6)); @@ -738,13 +738,13 @@ build_ssdt(GArray *table_data, GArray *linker, crs = aml_resource_template(); aml_append(crs, - aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) + aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) ); aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(dev, aml_operation_region("PEOR", aml_system_io, + aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, misc->pvpanic_port, 1)); - field = aml_field("PEOR", aml_byte_acc, aml_preserve); + field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE); aml_append(field, aml_named_field("PEPT", 8)); aml_append(dev, field); @@ -773,15 +773,15 @@ build_ssdt(GArray *table_data, GArray *linker, aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); crs = aml_resource_template(); aml_append(crs, - aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, + aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, pm->cpu_hp_io_len) ); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(sb_scope, dev); /* declare CPU hotplug MMIO region and PRS field to access it */ aml_append(sb_scope, aml_operation_region( - "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); - field = aml_field("PRST", aml_byte_acc, aml_preserve); + "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); + field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE); aml_append(field, aml_named_field("PRS", 256)); aml_append(sb_scope, field); @@ -845,18 +845,18 @@ build_ssdt(GArray *table_data, GArray *linker, crs = aml_resource_template(); aml_append(crs, - aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, + aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, pm->mem_hp_io_len) ); aml_append(scope, aml_name_decl("_CRS", crs)); aml_append(scope, aml_operation_region( - stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io, + stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, pm->mem_hp_io_base, pm->mem_hp_io_len) ); - field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc, - aml_preserve); + field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, + AML_PRESERVE); aml_append(field, /* read only */ aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); aml_append(field, /* read only */ @@ -869,8 +869,8 @@ build_ssdt(GArray *table_data, GArray *linker, aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); aml_append(scope, field); - field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc, - aml_write_as_zeros); + field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, + AML_WRITE_AS_ZEROS); aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); aml_append(field, /* 1 if enabled, read only */ aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); @@ -885,8 +885,8 @@ build_ssdt(GArray *table_data, GArray *linker, aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); aml_append(scope, field); - field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc, - aml_preserve); + field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, + AML_PRESERVE); aml_append(field, /* DIMM selector, write only */ aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); aml_append(field, /* _OST event code, write only */ diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 3947201..c0e81d4 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -36,49 +36,49 @@ struct Aml { typedef struct Aml Aml; typedef enum { - aml_decode10 = 0, - aml_decode16 = 1, + AML_DECODE10 = 0, + AML_DECODE16 = 1, } AmlIODecode; typedef enum { - aml_any_acc = 0, - aml_byte_acc = 1, - aml_word_acc = 2, - aml_dword_acc = 3, - aml_qword_acc = 4, - aml_buffer_acc = 5, + AML_ANY_ACC = 0, + AML_BYTE_ACC = 1, + AML_WORD_ACC = 2, + AML_DWORD_ACC = 3, + AML_QWORD_ACC = 4, + AML_BUFFER_ACC = 5, } AmlAccessType; typedef enum { - aml_preserve = 0, - aml_write_as_ones = 1, - aml_write_as_zeros = 2, + AML_PRESERVE = 0, + AML_WRITE_AS_ONES = 1, + AML_WRITE_AS_ZEROS = 2, } AmlUpdateRule; typedef enum { - aml_system_memory = 0x00, - aml_system_io = 0x01, + AML_SYSTEM_MEMORY = 0X00, + AML_SYSTEM_IO = 0X01, } AmlRegionSpace; typedef enum { - aml_memory_range = 0, - aml_io_range = 1, - aml_bus_number_range = 2, + AML_MEMORY_RANGE = 0, + AML_IO_RANGE = 1, + AML_BUS_NUMBER_RANGE = 2, } AmlResourceType; typedef enum { - aml_sub_decode = 1 << 1, - aml_pos_decode = 0 + AML_SUB_DECODE = 1 << 1, + AML_POS_DECODE = 0 } AmlDecode; typedef enum { - aml_max_fixed = 1 << 3, - aml_max_not_fixed = 0, + AML_MAX_FIXED = 1 << 3, + AML_MAX_NOT_FIXED = 0, } AmlMaxFixed; typedef enum { - aml_min_fixed = 1 << 2, - aml_min_not_fixed = 0 + AML_MIN_FIXED = 1 << 2, + AML_MIN_NOT_FIXED = 0 } AmlMinFixed; /* @@ -86,9 +86,9 @@ typedef enum { * _RNG field definition */ typedef enum { - aml_isa_only = 1, - aml_non_isa_only = 2, - aml_entire_range = 3, + AML_ISA_ONLY = 1, + AML_NON_ISA_ONLY = 2, + AML_ENTIRE_RANGE = 3, } AmlISARanges; /* @@ -96,19 +96,19 @@ typedef enum { * _MEM field definition */ typedef enum { - aml_non_cacheable = 0, - aml_cacheable = 1, - aml_write_combining = 2, - aml_prefetchable = 3, -} AmlCacheble; + AML_NON_CACHEABLE = 0, + AML_CACHEABLE = 1, + AML_WRITE_COMBINING = 2, + AML_PREFETCHABLE = 3, +} AmlCacheable; /* * ACPI 1.0b: Table 6-25 Memory Resource Flag (Resource Type = 0) Definitions * _RW field definition */ typedef enum { - aml_ReadOnly = 0, - aml_ReadWrite = 1, + AML_READ_ONLY = 0, + AML_READ_WRITE = 1, } AmlReadAndWrite; typedef @@ -191,13 +191,13 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed, uint16_t addr_max, uint16_t addr_trans, uint16_t len); Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed, - AmlMaxFixed max_fixed, AmlCacheble cacheable, + AmlMaxFixed max_fixed, AmlCacheable cacheable, AmlReadAndWrite read_and_write, uint32_t addr_gran, uint32_t addr_min, uint32_t addr_max, uint32_t addr_trans, uint32_t len); Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed, - AmlMaxFixed max_fixed, AmlCacheble cacheable, + AmlMaxFixed max_fixed, AmlCacheable cacheable, AmlReadAndWrite read_and_write, uint64_t addr_gran, uint64_t addr_min, uint64_t addr_max, uint64_t addr_trans,