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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id qw6si22597319pab.54.2015.05.19.11.33.40 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 19 May 2015 11:33:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YumKc-0001N1-NO; Tue, 19 May 2015 19:33:34 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, alex.bennee@linaro.org, agraf@suse.de, serge.fdrv@gmail.com, edgar.iglesias@xilinx.com Subject: [PATCH 12/14] target-arm: Move TB flags down to fill gap Date: Tue, 19 May 2015 19:33:32 +0100 Message-Id: <1432060414-5195-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1432060414-5195-1-git-send-email-peter.maydell@linaro.org> References: <1432060414-5195-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 647e0ba..dd7a90b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState *env) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime */ -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 +#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) /* Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -#define ARM_TBFLAG_NS_SHIFT 22 +#define ARM_TBFLAG_NS_SHIFT 19 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) /* Bit usage when in AArch64 state: currently we have no A64 specific bits */