From patchwork Mon May 18 19:15:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 48701 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id BB63D21411 for ; Mon, 18 May 2015 19:16:50 +0000 (UTC) Received: by wgtl5 with SMTP id l5sf57436037wgt.1 for ; Mon, 18 May 2015 12:16:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=Edf+wWHZ45mQoKp2Ny2FqKTscRvwYBvakC6ZKCYWaVo=; b=dwUiGlAkQYUluIthoUOc3UZyPuvnzDkM/ii+334LsjrtlHNmF4Mz/dt9XFLXo7aiWX i2Awm12sQfeiYpzpBt9SXxMm/Tuqdq1JOzISmuskdvxStXYXRx6HUzaD/CqvTwkQsRZW kILkmW2FbhFqJ6K5GrCWr6VIPqarB1njPTcY3RqR2CdscKpE3gibCJNVJsgnMunPL1uu jhnKOiNSOD+MBjFupt/0q03fo5VElzrrprthmTVBoARS13zhJgLbXsAYqrnANq2tkZ1r WzZmb8Bp+qwq1TvSG4zlwF4AAiHPQP2eTiBxAfOVbX5huEFsYnMeFIlI9SAxk1GkR/R+ 5AwA== X-Gm-Message-State: ALoCoQlsrdj52M8IrKe8gOf7CF8moDizG8157FOabE7ai90T1viNi+Kov3Ovce7kDWTY54l7Qjji X-Received: by 10.112.53.102 with SMTP id a6mr18851585lbp.16.1431976609754; Mon, 18 May 2015 12:16:49 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.23.74 with SMTP id k10ls804204laf.30.gmail; Mon, 18 May 2015 12:16:49 -0700 (PDT) X-Received: by 10.112.130.129 with SMTP id oe1mr9562577lbb.37.1431976609542; Mon, 18 May 2015 12:16:49 -0700 (PDT) Received: from mail-la0-f43.google.com (mail-la0-f43.google.com. [209.85.215.43]) by mx.google.com with ESMTPS id pf2si7289075lbc.2.2015.05.18.12.16.49 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 May 2015 12:16:49 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) client-ip=209.85.215.43; Received: by laat2 with SMTP id t2so233903328laa.1 for ; Mon, 18 May 2015 12:16:49 -0700 (PDT) X-Received: by 10.112.13.6 with SMTP id d6mr18178988lbc.117.1431976609454; Mon, 18 May 2015 12:16:49 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp280428lbb; Mon, 18 May 2015 12:16:48 -0700 (PDT) X-Received: by 10.55.24.209 with SMTP id 78mr27356989qky.19.1431976607440; Mon, 18 May 2015 12:16:47 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 144si11206565qhw.119.2015.05.18.12.16.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 18 May 2015 12:16:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:42639 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQWs-0002hA-0Q for patch@linaro.org; Mon, 18 May 2015 15:16:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQVd-0001Wy-UU for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YuQVc-0008Ra-NL for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:29 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YuQVc-0008QT-9A for qemu-devel@nongnu.org; Mon, 18 May 2015 15:15:28 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YuQVV-0007u9-68 for qemu-devel@nongnu.org; Mon, 18 May 2015 20:15:21 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 18 May 2015 20:15:02 +0100 Message-Id: <1431976521-30352-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1431976521-30352-1-git-send-email-peter.maydell@linaro.org> References: <1431976521-30352-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 02/21] target-arm: cpu64: Add support for Cortex-A53 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Peter Crosthwaite Add the ARM Cortex-A53 processor definition. Similar to A57, but with different L1 I cache policy, phys addr size and different cache geometries. The cache sizes is implementation configurable, but use these values (from Xilinx Zynq MPSoC) as a default until cache size configurability is added. Acked-by: Edgar E. Iglesias Reviewed-by: Peter Maydell Signed-off-by: Peter Crosthwaite Message-id: db439ff834cf0431bc192b05272a3b28fe2045d0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- target-arm/cpu64.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 13e042e..bf7dd68 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -143,6 +143,56 @@ static void aarch64_a57_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +static void aarch64_a53_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a53"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + cpu->midr = 0x410fd034; + cpu->reset_fpsid = 0x41034070; + cpu->mvfr0 = 0x10110222; + cpu->mvfr1 = 0x12111111; + cpu->mvfr2 = 0x00000043; + cpu->ctr = 0x84448004; /* L1Ip = VIPT */ + cpu->reset_sctlr = 0x00c50838; + cpu->id_pfr0 = 0x00000131; + cpu->id_pfr1 = 0x00011011; + cpu->id_dfr0 = 0x03010066; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10101105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02102211; + cpu->id_isar0 = 0x02101110; + cpu->id_isar1 = 0x13112111; + cpu->id_isar2 = 0x21232042; + cpu->id_isar3 = 0x01112131; + cpu->id_isar4 = 0x00011142; + cpu->id_isar5 = 0x00011121; + cpu->id_aa64pfr0 = 0x00002222; + cpu->id_aa64dfr0 = 0x10305106; + cpu->id_aa64isar0 = 0x00011120; + cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ + cpu->dbgdidr = 0x3516d000; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); +} + #ifdef CONFIG_USER_ONLY static void aarch64_any_initfn(Object *obj) { @@ -170,6 +220,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, + { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = aarch64_any_initfn }, #endif