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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id c198si22378653qka.100.2015.05.14.02.31.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 14 May 2015 02:31:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:53341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YspUh-0008Kq-8q for patch@linaro.org; Thu, 14 May 2015 05:31:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YspNX-0005IW-EE for qemu-devel@nongnu.org; Thu, 14 May 2015 05:24:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YspNT-0001Aj-6o for qemu-devel@nongnu.org; Thu, 14 May 2015 05:24:31 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:32395) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YspNS-00018V-Im for qemu-devel@nongnu.org; Thu, 14 May 2015 05:24:27 -0400 Received: from 172.24.2.119 (EHLO szxeml430-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CLJ60754; Thu, 14 May 2015 17:20:59 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml430-hub.china.huawei.com (10.82.67.185) with Microsoft SMTP Server id 14.3.158.1; Thu, 14 May 2015 17:20:49 +0800 From: Shannon Zhao To: , , , , , , , , , , Date: Thu, 14 May 2015 17:19:23 +0800 Message-ID: <1431595182-7552-5-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1431595182-7552-1-git-send-email-zhaoshenglong@huawei.com> References: <1431595182-7552-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.65 Cc: hangaohuai@huawei.com, zhaoshenglong@huawei.com, peter.huangpeng@huawei.com, shannon.zhao@linaro.org Subject: [Qemu-devel] [PATCH v7 04/23] hw/acpi/aml-build: Add aml_memory32_fixed() term X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add aml_memory32_fixed() for describing device mmio region in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée --- hw/acpi/aml-build.c | 25 +++++++++++++++++++++++++ include/hw/acpi/aml-build.h | 2 ++ 2 files changed, 27 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 77ce00b..ce68d27 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -26,6 +26,7 @@ #include #include "hw/acpi/aml-build.h" #include "qemu/bswap.h" +#include "qemu/bitops.h" #include "hw/acpi/bios-linker-loader.h" static GArray *build_alloc_array(void) @@ -48,6 +49,14 @@ static void build_append_byte(GArray *array, uint8_t val) g_array_append_val(array, val); } +static void build_append_uint32(GArray *array, uint32_t val) +{ + build_append_byte(array, extract32(val, 0, 8)); + build_append_byte(array, extract32(val, 8, 8)); + build_append_byte(array, extract32(val, 16, 8)); + build_append_byte(array, extract32(val, 24, 8)); +} + static void build_append_array(GArray *array, GArray *val) { g_array_append_vals(array, val->data, val->len); @@ -505,6 +514,22 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4) return var; } +/* + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro) + */ +Aml *aml_memory32_fixed(uint32_t addr, uint32_t size, + AmlReadAndWrite read_and_write) +{ + Aml *var = aml_alloc(); + build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */ + build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */ + build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */ + build_append_byte(var->buf, read_and_write); /* Write status, 1 rw 0 ro */ + build_append_uint32(var->buf, addr); /* Range base address */ + build_append_uint32(var->buf, size); /* Range length */ + return var; +} + /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */ Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 3947201..b1413a3 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -168,6 +168,8 @@ Aml *aml_call1(const char *method, Aml *arg1); Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2); Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3); Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4); +Aml *aml_memory32_fixed(uint32_t addr, uint32_t size, + AmlReadAndWrite read_and_write); Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len); Aml *aml_operation_region(const char *name, AmlRegionSpace rs,