From patchwork Mon May 11 13:40:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 48298 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 679DE21550 for ; Mon, 11 May 2015 13:49:42 +0000 (UTC) Received: by wgiv13 with SMTP id v13sf39249408wgi.3 for ; Mon, 11 May 2015 06:49:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=m3bBWBg83ZZIXaZH1eVY/PdLd2AiuAP4JagmrSCXLhg=; b=W8FFP3FqQ+kLxLB06qMZ4Y3imbjnAUwoHemI8SdUHuePiRF8hZsAO3FMjDdA5hpoZB PuL16xQLp2MWs2ultTEjrxvvh1beh7ztildhiLy74+L/v19s52zTbShhMgrwXU/Z955k HKrSwjSj1TQpxb9uwcVuKZn9HAoe91zggD+UBUVecw8F/DMJ+tGUZaSxkjzTFotbBRvS KVZKNAFscdlh6v+bAnA6fw5iVJHFiEjXp0Jo0mc4QRTfgIUwMuOaEM7jdW4uuyMUg+5T 5isaQzbpuORdJiTVforV6Sp5JGFICx4LWu7VihNQMt5S5H2OwJAmtx2sHh+1wsUJqW0R smjw== X-Gm-Message-State: ALoCoQlhqflgRJGwbRGtJvwKsySELhKsxR5qGGZN5w21qbyimZzf+cQruENgVaKyjmdGjxOT53Fe X-Received: by 10.112.26.5 with SMTP id h5mr7548422lbg.4.1431352181761; Mon, 11 May 2015 06:49:41 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.153.7.167 with SMTP id dd7ls535773lad.28.gmail; Mon, 11 May 2015 06:49:41 -0700 (PDT) X-Received: by 10.152.115.203 with SMTP id jq11mr8019104lab.115.1431352181624; Mon, 11 May 2015 06:49:41 -0700 (PDT) Received: from mail-la0-f43.google.com (mail-la0-f43.google.com. [209.85.215.43]) by mx.google.com with ESMTPS id eq9si8378426lac.131.2015.05.11.06.49.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 May 2015 06:49:41 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) client-ip=209.85.215.43; Received: by layy10 with SMTP id y10so93594049lay.0 for ; Mon, 11 May 2015 06:49:41 -0700 (PDT) X-Received: by 10.152.4.137 with SMTP id k9mr8040940lak.29.1431352181471; Mon, 11 May 2015 06:49:41 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp1517336lbb; Mon, 11 May 2015 06:49:40 -0700 (PDT) X-Received: by 10.55.20.136 with SMTP id 8mr22158240qku.16.1431352178401; Mon, 11 May 2015 06:49:38 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 35si12975504qgt.121.2015.05.11.06.49.37 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 11 May 2015 06:49:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:37511 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro5R-0000uD-By for patch@linaro.org; Mon, 11 May 2015 09:49:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yrnww-0002OT-2i for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yrnwu-0000gY-HO for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:49 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34139) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yrnwu-0000ZY-3j for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:48 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Yrnwl-0005fO-7X for qemu-devel@nongnu.org; Mon, 11 May 2015 14:40:39 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 11 May 2015 14:40:32 +0100 Message-Id: <1431351638-21705-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1431351638-21705-1-git-send-email-peter.maydell@linaro.org> References: <1431351638-21705-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 13/19] hw/intc/arm_gic: Handle grouping for GICC_HPPIR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Grouping (GICv2) and Security Extensions change the behaviour of reads of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell Message-id: 1430502643-25909-12-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-12-git-send-email-greg.bellows@linaro.org [PMM: make utility fn static; coding style fixes; AckCtl has an effect for GICv2 without security extensions as well; removed checks on enable bits because these are done when we set current_pending[cpu]] Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 7c0ddc8..75c69b3 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -176,6 +176,32 @@ static void gic_set_irq(void *opaque, int irq, int level) gic_update(s); } +static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, + MemTxAttrs attrs) +{ + uint16_t pending_irq = s->current_pending[cpu]; + + if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { + int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); + /* On a GIC without the security extensions, reading this register + * behaves in the same way as a secure access to a GIC with them. + */ + bool secure = !s->security_extn || attrs.secure; + + if (group == 0 && !secure) { + /* Group0 interrupts hidden from Non-secure access */ + return 1023; + } + if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { + /* Group1 interrupts only seen by Secure access if + * AckCtl bit set. + */ + return 1022; + } + } + return pending_irq; +} + static void gic_set_running_irq(GICState *s, int cpu, int irq) { s->running_irq[cpu] = irq; @@ -890,7 +916,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, *data = gic_get_running_priority(s, cpu, attrs); break; case 0x18: /* Highest Pending Interrupt */ - *data = s->current_pending[cpu]; + *data = gic_get_current_pending_irq(s, cpu, attrs); break; case 0x1c: /* Aliased Binary Point */ /* GIC v2, no security: ABPR