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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id n9si1452334qkh.16.2015.05.07.02.34.54 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 07 May 2015 02:34:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:49671 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqICj-0002nI-Qq for patch@linaro.org; Thu, 07 May 2015 05:34:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56549) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqI9n-0006u4-Qn for qemu-devel@nongnu.org; Thu, 07 May 2015 05:31:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YqI9l-0001k6-N2 for qemu-devel@nongnu.org; Thu, 07 May 2015 05:31:51 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:52317) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqI9l-0001fo-3x for qemu-devel@nongnu.org; Thu, 07 May 2015 05:31:49 -0400 Received: from 172.24.2.119 (EHLO szxeml426-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CKZ44922; Thu, 07 May 2015 17:31:27 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.158.1; Thu, 7 May 2015 17:31:20 +0800 From: Shannon Zhao To: , , , , , , , , , , Date: Thu, 7 May 2015 17:29:06 +0800 Message-ID: <1430990964-10528-5-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1430990964-10528-1-git-send-email-zhaoshenglong@huawei.com> References: <1430990964-10528-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.65 Cc: hangaohuai@huawei.com, zhaoshenglong@huawei.com, peter.huangpeng@huawei.com, shannon.zhao@linaro.org Subject: [Qemu-devel] [PATCH v6 04/22] hw/acpi/aml-build: Add aml_memory32_fixed() term X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add aml_memory32_fixed() for describing device mmio region in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao Reviewed-by: Alex Bennée --- hw/acpi/aml-build.c | 27 +++++++++++++++++++++++++++ include/hw/acpi/aml-build.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 8d01959..61407b7 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -26,6 +26,7 @@ #include #include "hw/acpi/aml-build.h" #include "qemu/bswap.h" +#include "qemu/bitops.h" #include "hw/acpi/bios-linker-loader.h" static GArray *build_alloc_array(void) @@ -505,6 +506,32 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4) return var; } +/* + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro) + */ +Aml *aml_memory32_fixed(uint32_t addr, uint32_t size, + AmlReadAndWrite read_and_write) +{ + Aml *var = aml_alloc(); + build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */ + build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */ + build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */ + build_append_byte(var->buf, read_and_write); /* Write status, 1 rw 0 ro */ + + /* Range base address */ + build_append_byte(var->buf, extract32(addr, 0, 8)); /* bits[7:0] */ + build_append_byte(var->buf, extract32(addr, 8, 8)); /* bits[15:8] */ + build_append_byte(var->buf, extract32(addr, 16, 8)); /* bits[23:16] */ + build_append_byte(var->buf, extract32(addr, 24, 8)); /* bits[31:24] */ + + /* Range length */ + build_append_byte(var->buf, extract32(size, 0, 8)); /* bits[7:0] */ + build_append_byte(var->buf, extract32(size, 8, 8)); /* bits[15:8] */ + build_append_byte(var->buf, extract32(size, 16, 8)); /* bits[23:16] */ + build_append_byte(var->buf, extract32(size, 24, 8)); /* bits[31:24] */ + return var; +} + /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */ Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 1705001..154823b 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -162,6 +162,8 @@ Aml *aml_call1(const char *method, Aml *arg1); Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2); Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3); Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4); +Aml *aml_memory32_fixed(uint32_t addr, uint32_t size, + AmlReadAndWrite read_and_write); Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len); Aml *aml_operation_region(const char *name, AmlRegionSpace rs,