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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id pi9si8825910wic.96.2015.05.01.10.50.51 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 01 May 2015 10:50:52 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YoF5I-0006lN-AL; Fri, 01 May 2015 18:50:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Greg Bellows , "Edgar E. Iglesias" Subject: [PATCH v4 16/17] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC Date: Fri, 1 May 2015 18:50:42 +0100 Message-Id: <1430502643-25909-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> References: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Fabian Aggeler Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Message-id: 1429113742-8371-3-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: Peter Maydell --- hw/arm/vexpress.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 3989bc5..8f1a5ea 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -253,6 +253,8 @@ static void init_cpus(const char *cpu_model, const char *privdev, DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(busdev, n + smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); } }