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[99.179.1.214]) by mx.google.com with ESMTPSA id w72sm3417636oie.28.2015.04.22.10.09.34 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 22 Apr 2015 10:09:35 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Wed, 22 Apr 2015 12:09:14 -0500 Message-Id: <1429722561-12651-3-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1429722561-12651-1-git-send-email-greg.bellows@linaro.org> References: <1429722561-12651-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.170 Cc: serge.fdrv@gmail.com, Greg Bellows Subject: [Qemu-devel] [PATCH v2 2/9] target-arm: Extend helpers to route exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Updated the various helper routines to set the target EL as needed using a dedicated function. Signed-off-by: Greg Bellows --- v1 -> v2 - Add utility function for determining the target exception EL. - Replaced uses of MAX with the above function when setting the target EL. --- target-arm/op_helper.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 72a973a..971edc7 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -33,6 +33,20 @@ static void raise_exception(CPUARMState *env, int tt) cpu_loop_exit(cs); } +static int exception_target_el(CPUARMState *env) +{ + int target_el = MAX(1, arm_current_el(env)); + + /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL + * to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, uint32_t rn, uint32_t maxindex) { @@ -306,6 +320,7 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome) if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { env->exception.syndrome = syndrome; + env->exception.target_el = exception_target_el(env); raise_exception(env, EXCP_UDEF); } @@ -363,6 +378,7 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) * to catch that case at translate time. */ if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { + env->exception.target_el = exception_target_el(env); raise_exception(env, EXCP_UDEF); } @@ -422,6 +438,7 @@ void HELPER(pre_hvc)(CPUARMState *env) if (undef) { env->exception.syndrome = syn_uncategorized(); + env->exception.target_el = exception_target_el(env); raise_exception(env, EXCP_UDEF); } } @@ -452,11 +469,13 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */ env->exception.syndrome = syndrome; + env->exception.target_el = 2; raise_exception(env, EXCP_HYP_TRAP); } if (undef) { env->exception.syndrome = syn_uncategorized(); + env->exception.target_el = exception_target_el(env); raise_exception(env, EXCP_UDEF); } }