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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id bn4si14757648wib.52.2015.04.07.13.10.11 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 07 Apr 2015 13:10:12 -0700 (PDT) Received-SPF: none (google.com: pm215@archaic.org.uk does not designate permitted sender hosts) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YfZov-0002Dv-8Q; Tue, 07 Apr 2015 21:10:01 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Greg Bellows , Paolo Bonzini , Richard Henderson , "Edgar E. Iglesias" , Peter Crosthwaite , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 12/14] target-arm: Add user-mode transaction attribute Date: Tue, 7 Apr 2015 21:09:58 +0100 Message-Id: <1428437400-8474-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1428437400-8474-1-git-send-email-peter.maydell@linaro.org> References: <1428437400-8474-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add a transaction attribute indicating that a memory access is being done from user-mode (unprivileged). This corresponds to an equivalent signal in ARM AMBA buses. Signed-off-by: Peter Maydell --- include/exec/memattrs.h | 3 +++ target-arm/helper.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 5df180e..458c0ea 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -27,6 +27,9 @@ typedef uint64_t MemTxAttrs; /* ARM/AMBA TrustZone Secure access */ #define MEMTXATTRS_SECURE (1ULL << 0) +/* Memory access is usermode (unprivileged) */ +#define MEMTXATTRS_USER (1ULL << 1) + /* Bus masters which don't specify any attributes will get this, * which has all attribute bits clear except the topmost one * (so that we can distinguish "all attributes deliberately clear" diff --git a/target-arm/helper.c b/target-arm/helper.c index fdeb2b7..6fca8f8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5752,6 +5752,10 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, *attrs = 0; } + if (regime_is_user(env, mmu_idx)) { + *attrs |= MEMTXATTRS_USER; + } + /* Fast Context Switch Extension. This doesn't exist at all in v8. * In v7 and earlier it affects all stage 1 translations. */