From patchwork Fri Apr 3 10:03:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 46744 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f197.google.com (mail-wi0-f197.google.com [209.85.212.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8D39E216D1 for ; Fri, 3 Apr 2015 10:07:34 +0000 (UTC) Received: by wibgr10 with SMTP id gr10sf23807773wib.2 for ; Fri, 03 Apr 2015 03:07:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:content-type:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=EQCv0M+U4Z+UAgIiw79KOiUV85Mjq4Jh1QNfksjRlP4=; b=EbFY24Aan5wXmNF/W81wFVJYxs5r1HDyxjfdvPHLsuns7Qksk5xAxieyqhqlAfkBCl qGLzHeY4fcxPNLrMTwU8fiPiI+tHyRosihG0rNwz6KU1boSXnxQp9X8jEJFXfx5clt+O GBHKmGh8sm7G40jKDtcba4KqMCQgiwrk9nJIgv7So/EWNjIsYOmK1u4AcZ5Kc+jbCXu/ F3BnPJhubs+Muw50+F46y5L8qagW2Q5Mna4Yag72J1x8Z1bNRyUUf17fpFSfTahP8Do7 pvt7UqKZilehyoCdGqiSdJUQGv/NXr73iWxpsyAp6TbJ5j1rAONCb7xLXPmqFhPzkOM0 FWIQ== X-Gm-Message-State: ALoCoQn8WuoLVLeYZA6cq4QwNLZMbQ0mw4pSzREtsyhpBDL6041UgDsw8gmWmypERY13gFrXwXDT X-Received: by 10.180.88.196 with SMTP id bi4mr4156540wib.5.1428055653826; Fri, 03 Apr 2015 03:07:33 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.136 with SMTP id s8ls313129las.5.gmail; Fri, 03 Apr 2015 03:07:33 -0700 (PDT) X-Received: by 10.112.149.10 with SMTP id tw10mr1573050lbb.78.1428055653669; Fri, 03 Apr 2015 03:07:33 -0700 (PDT) Received: from mail-la0-f47.google.com (mail-la0-f47.google.com. [209.85.215.47]) by mx.google.com with ESMTPS id bf6si6341746lbc.57.2015.04.03.03.07.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Apr 2015 03:07:33 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) client-ip=209.85.215.47; Received: by lagv1 with SMTP id v1so1172614lag.3 for ; Fri, 03 Apr 2015 03:07:33 -0700 (PDT) X-Received: by 10.152.23.70 with SMTP id k6mr1521685laf.76.1428055653217; Fri, 03 Apr 2015 03:07:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.57.201 with SMTP id k9csp1858541lbq; Fri, 3 Apr 2015 03:07:32 -0700 (PDT) X-Received: by 10.55.43.14 with SMTP id r14mr2856369qkh.35.1428055651983; Fri, 03 Apr 2015 03:07:31 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p64si7713620qha.8.2015.04.03.03.07.31 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 03 Apr 2015 03:07:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:33272 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YdyVf-0003GM-1P for patch@linaro.org; Fri, 03 Apr 2015 06:07:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38205) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YdyUS-0001ZV-2E for qemu-devel@nongnu.org; Fri, 03 Apr 2015 06:06:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YdyUO-0005zv-S6 for qemu-devel@nongnu.org; Fri, 03 Apr 2015 06:06:15 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:9545) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YdyUO-0005kE-90 for qemu-devel@nongnu.org; Fri, 03 Apr 2015 06:06:12 -0400 Received: from 172.24.2.119 (EHLO szxeml425-hub.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BDZ47781; Fri, 03 Apr 2015 18:05:49 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml425-hub.china.huawei.com (10.82.67.180) with Microsoft SMTP Server id 14.3.158.1; Fri, 3 Apr 2015 18:05:40 +0800 From: Shannon Zhao To: , , , , , , , , , , Date: Fri, 3 Apr 2015 18:03:36 +0800 Message-ID: <1428055432-12120-5-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1428055432-12120-1-git-send-email-zhaoshenglong@huawei.com> References: <1428055432-12120-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.551E65FD.01BD, ss=1, re=0.001, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 107b8e4df7f1a14febcb394064092abf X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.66 Cc: hangaohuai@huawei.com, shannon.zhao@linaro.org, peter.huangpeng@huawei.com, zhaoshenglong@huawei.com Subject: [Qemu-devel] [PATCH v4 04/20] hw/acpi/aml-build: Add aml_memory32_fixed() term X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add aml_memory32_fixed() for describing device mmio region in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao --- hw/acpi/aml-build.c | 22 ++++++++++++++++++++++ include/hw/acpi/aml-build.h | 1 + 2 files changed, 23 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 8d01959..fefe7c7 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -505,6 +505,28 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4) return var; } +/* + * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro) + */ +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag) +{ + Aml *var = aml_alloc(); + build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */ + build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */ + build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */ + build_append_byte(var->buf, rw_flag); /* Write status, 1 rw 0 ro */ + build_append_byte(var->buf, addr & 0xff); /* Range base address bits[7:0] */ + build_append_byte(var->buf, (addr >> 8) & 0xff); /* Range base address bits[15:8] */ + build_append_byte(var->buf, (addr >> 16) & 0xff); /* Range base address bits[23:16] */ + build_append_byte(var->buf, (addr >> 24) & 0xff); /* Range base address bits[31:24] */ + + build_append_byte(var->buf, size & 0xff); /* Range length bits[7:0] */ + build_append_byte(var->buf, (size >> 8) & 0xff); /* Range length bits[15:8] */ + build_append_byte(var->buf, (size >> 16) & 0xff); /* Range length bits[23:16] */ + build_append_byte(var->buf, (size >> 24) & 0xff); /* Range length bits[31:24] */ + return var; +} + /* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */ Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 1705001..baa0652 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -162,6 +162,7 @@ Aml *aml_call1(const char *method, Aml *arg1); Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2); Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3); Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4); +Aml *aml_memory32_fixed(uint64_t addr, uint64_t size, uint8_t rw_flag); Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base, uint8_t aln, uint8_t len); Aml *aml_operation_region(const char *name, AmlRegionSpace rs,