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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 80si1269377qkr.69.2015.03.23.10.08.13 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 23 Mar 2015 10:08:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:57171 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ya5pk-0000ip-JQ for patch@linaro.org; Mon, 23 Mar 2015 13:08:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52187) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ya5n7-0005E5-68 for qemu-devel@nongnu.org; Mon, 23 Mar 2015 13:05:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ya5my-0005z4-8X for qemu-devel@nongnu.org; Mon, 23 Mar 2015 13:05:29 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:35912 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ya5my-0005yr-3i for qemu-devel@nongnu.org; Mon, 23 Mar 2015 13:05:20 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaroharston) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1Ya6rF-0005wQ-7o; Mon, 23 Mar 2015 19:13:49 +0100 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 23 Mar 2015 17:05:43 +0000 Message-Id: <1427130344-27986-6-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.3.2 In-Reply-To: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org> References: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: Peter Maydell , kvm@vger.kernel.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v5 5/6] target-arm: kvm64 fix save/restore of SPSR regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The current code was negatively indexing the cpu state array and not synchronizing banked spsr register state with the current mode's spsr state, causing occasional failures with migration. Some munging is done to take care of the aarch64 mapping and also to ensure the most current value of the spsr is updated to the banked registers (relevant for KVM<->TCG migration). Signed-off-by: Alex BennĂ©e --- v2 (ajb) - minor tweaks and clarifications v3 - Use the correct bank index function for setting/getting env->spsr - only deal with spsrs in elevated exception levels v4 - try and make commentary clearer - ensure env->banked_spsr[0] = env->spsr before we sync v5 - fix banking index now banking fixed - keep wide spacing on [ ] forms - claimed authorship diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 857e970..5270fa7 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -139,6 +139,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) uint64_t val; int i; int ret; + unsigned int el; ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -205,9 +206,24 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } + /* Saved Program State Registers + * + * Before we restore from the banked_spsr[] array we need to + * ensure that any modifications to env->spsr are correctly + * reflected in the banks. + */ + el = arm_current_el(env); + if (el > 0) { + i = is_a64(env) ? + aarch64_banked_spsr_index(el) : + bank_number(env->uncached_cpsr & CPSR_M); + env->banked_spsr[i] = env->spsr; + } + + /* KVM 0-4 map to QEMU banks 1-5 */ for (i = 0; i < KVM_NR_SPSR; i++) { reg.id = AARCH64_CORE_REG(spsr[i]); - reg.addr = (uintptr_t) &env->banked_spsr[i - 1]; + reg.addr = (uintptr_t) &env->banked_spsr[i + 1]; ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; @@ -253,11 +269,13 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } + int kvm_arch_get_registers(CPUState *cs) { struct kvm_one_reg reg; uint64_t val; uint32_t fpr; + unsigned int el; int i; int ret; @@ -330,15 +348,27 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } + /* Fetch the SPSR registers + * + * KVM SPSRs 0-4 map to QEMU banks 1-5 + */ for (i = 0; i < KVM_NR_SPSR; i++) { reg.id = AARCH64_CORE_REG(spsr[i]); - reg.addr = (uintptr_t) &env->banked_spsr[i - 1]; + reg.addr = (uintptr_t) &env->banked_spsr[i + 1]; ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); if (ret) { return ret; } } + el = arm_current_el(env); + if (el > 0) { + i = is_a64(env) ? + aarch64_banked_spsr_index(el) : + bank_number(env->uncached_cpsr & CPSR_M); + env->spsr = env->banked_spsr[i]; + } + /* Advanced SIMD and FP registers * We map Qn = regs[2n+1]:regs[2n] */