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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 88si9544328qkw.124.2015.03.16.04.09.33 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 16 Mar 2015 04:09:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:48418 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXStp-0002yk-LP for patch@linaro.org; Mon, 16 Mar 2015 07:09:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50924) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXSr7-0007Ny-Rs for qemu-devel@nongnu.org; Mon, 16 Mar 2015 07:06:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YXSr2-0007AA-2h for qemu-devel@nongnu.org; Mon, 16 Mar 2015 07:06:45 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:33337 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXSr1-00079s-TM for qemu-devel@nongnu.org; Mon, 16 Mar 2015 07:06:40 -0400 Received: from localhost ([127.0.0.1] helo=zen.linaroharston) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1YXTtZ-0000VG-37; Mon, 16 Mar 2015 13:13:21 +0100 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 16 Mar 2015 11:01:56 +0000 Message-Id: <1426503716-13931-6-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.3.2 In-Reply-To: <1426503716-13931-1-git-send-email-alex.bennee@linaro.org> References: <1426503716-13931-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: Peter Maydell , kvm@vger.kernel.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 5/5] target-arm: cpu.h document why env->spsr exists X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 I was getting very confused about the duplication of state so wanted to make it explicit. Signed-off-by: Alex Bennée diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 083211c..6dc1799 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -155,6 +155,11 @@ typedef struct CPUARMState { This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ uint32_t uncached_cpsr; + /* The spsr is a alias for spsr_elN where N is the current + * exception level. It is provided for here so the TCG msr/mrs + * implementation can access one register. Care needs to be taken + * to ensure the banked_spsr[] is also updated. + */ uint32_t spsr; /* Banked registers. */