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[209.85.212.171]) by mx.google.com with ESMTPS id r17si14266412wib.12.2015.03.11.10.17.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Mar 2015 10:17:30 -0700 (PDT) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 209.85.212.171 as permitted sender) client-ip=209.85.212.171; Received: by wiwl15 with SMTP id l15so13666941wiw.0 for ; Wed, 11 Mar 2015 10:17:30 -0700 (PDT) X-Received: by 10.180.108.177 with SMTP id hl17mr122863833wib.35.1426094250504; Wed, 11 Mar 2015 10:17:30 -0700 (PDT) Received: from midway01-04-00.lavalab ([81.128.185.50]) by mx.google.com with ESMTPSA id dn7sm25636500wid.12.2015.03.11.10.17.29 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 11 Mar 2015 10:17:29 -0700 (PDT) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: christoffer.dall@linaro.org, kvmarm@lists.cs.columbia.edu, patches@linaro.org Subject: [PATCH v5] hw/intc/arm_gic: Initialize the vgic in the realize function Date: Wed, 11 Mar 2015 17:17:06 +0000 Message-Id: <1426094226-8515-1-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.8.3.2 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: eric.auger@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch forces vgic initialization in the vgic realize function. It uses a new group/attribute that allows such operation: KVM_DEV_ARM_VGIC_GRP_CTRL/KVM_DEV_ARM_VGIC_CTRL_INIT This earlier initialization allows, for example, to setup VFIO signaling and irqfd after vgic initialization, on a reset notifier. Signed-off-by: Eric Auger --- v4 -> v5: - add a comment to clarify what the new gic accesses aim at - header sync removed. The series becomes a singleton. v1 -> v2: - The init is not mandated to be done in a machine init done notifier anymore since only the number of vcpus and number of IRQs must be known at init time. --- hw/intc/arm_gic_kvm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 1ad3eb0..0d20750 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -573,6 +573,13 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, 0, &numirqs, 1); } + /* Tell the kernel to complete VGIC initialization now */ + if (kvm_gic_supports_attr(s, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CTRL_INIT)) { + kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_CTRL_INIT, 0, 0, 1); + } + /* Distributor */ memory_region_init_reservation(&s->iomem, OBJECT(s), "kvm-gic_dist", 0x1000);