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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 85si911692qhx.62.2015.02.25.08.03.52 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 25 Feb 2015 08:03:53 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:54759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeRE-0003XB-CW for patch@linaro.org; Wed, 25 Feb 2015 11:03:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47455) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQI-0002cT-Ak for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YQeQD-0006uP-Ny for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:54 -0500 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:47151 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQD-0006uG-It for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:49 -0500 Received: from localhost ([127.0.0.1] helo=zen.linaroharston) by socrates.bennee.com with esmtp (Exim 4.80) (envelope-from ) id 1YQfOE-0007hX-Qh; Wed, 25 Feb 2015 18:04:51 +0100 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 25 Feb 2015 16:02:38 +0000 Message-Id: <1424880159-29348-7-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> References: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: alex.bennee@linaro.org X-SA-Exim-Scanned: No (on socrates.bennee.com); SAEximRunCond expanded to false X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.71.155 Cc: Peter Maydell , kvm@vger.kernel.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH 5/6] target-arm/kvm64: fix save/restore of SPSR regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: alex.bennee@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.54 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Christoffer Dall The current code was negatively indexing the cpu state array and not synchronizing banked spsr register state with the current mode's spsr state, causing occasional failures with migration. Some munging is done to take care of the aarch64 mapping and also to ensure the most current value of the spsr is updated to the banked registers (relevant for KVM<->TCG migration). Signed-off-by: Christoffer Dall Signed-off-by: Alex BennĂ©e --- v2 (ajb) - minor tweaks and clarifications diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index c60e989..1e36b0a 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -140,6 +140,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) uint64_t val; int i; int ret; + unsigned int el; ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -206,9 +207,25 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } + /* Saved Program State Registers + * + * Before we restore from the banked_spsr[] array we need to + * ensure that any modifications to env->spsr are correctly + * reflected and map aarch64 exception levels if required. + */ + el = arm_current_el(env); + if (is_a64(env) && el > 0) { + g_assert(el == 1); + /* KVM maps KVM_SPSR_SVC to KVM_SPSR_EL1 for aarch64 */ + env->banked_spsr[1] = env->banked_spsr[0]; + env->banked_spsr[aarch64_banked_spsr_index(el)] = env->spsr; + } else { + env->banked_spsr[el] = env->spsr; + } + for (i = 0; i < KVM_NR_SPSR; i++) { reg.id = AARCH64_CORE_REG(spsr[i]); - reg.addr = (uintptr_t) &env->banked_spsr[i - 1]; + reg.addr = (uintptr_t) &env->banked_spsr[i+1]; ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; @@ -253,6 +270,7 @@ int kvm_arch_get_registers(CPUState *cs) struct kvm_one_reg reg; uint64_t val; uint32_t fpr; + unsigned int el; int i; int ret; @@ -325,15 +343,32 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } + /* Fetch the SPSR registers + * + * KVM has an array of state indexed for all the possible aarch32 + * privilage levels. Although not all are valid at all points + * there are some transitions possible which can access old state + * so it is worth keeping them all. + */ for (i = 0; i < KVM_NR_SPSR; i++) { reg.id = AARCH64_CORE_REG(spsr[i]); - reg.addr = (uintptr_t) &env->banked_spsr[i - 1]; + reg.addr = (uintptr_t) &env->banked_spsr[i+1]; ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); if (ret) { return ret; } } + el = arm_current_el(env); + if (is_a64(env) && el > 0) { + g_assert(el == 1); + /* KVM maps KVM_SPSR_SVC to KVM_SPSR_EL1 for aarch64 */ + env->banked_spsr[0] = env->banked_spsr[1]; + env->spsr = env->banked_spsr[aarch64_banked_spsr_index(el)]; + } else { + env->spsr = env->banked_spsr[el]; + } + /* Advanced SIMD and FP registers */ for (i = 0; i < 32; i++) { reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);