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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id ek10si4071416qcb.8.2015.02.11.22.50.44 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 11 Feb 2015 22:50:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:48726 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLnbn-0007Ga-R6 for patch@linaro.org; Thu, 12 Feb 2015 01:50:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41075) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLnaj-000654-IB for qemu-devel@nongnu.org; Thu, 12 Feb 2015 01:49:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YLnae-0000P9-Hy for qemu-devel@nongnu.org; Thu, 12 Feb 2015 01:49:37 -0500 Received: from mail-ie0-f170.google.com ([209.85.223.170]:37188) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLnae-0000P4-ED for qemu-devel@nongnu.org; Thu, 12 Feb 2015 01:49:32 -0500 Received: by iecrl12 with SMTP id rl12so7402067iec.4 for ; Wed, 11 Feb 2015 22:49:32 -0800 (PST) X-Received: by 10.50.61.201 with SMTP id s9mr2792257igr.0.1423723772012; Wed, 11 Feb 2015 22:49:32 -0800 (PST) Received: from localhost.localdomain ([113.28.134.59]) by mx.google.com with ESMTPSA id b6sm713096igb.15.2015.02.11.22.49.29 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 11 Feb 2015 22:49:31 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org, alex.bennee@linaro.org Date: Thu, 12 Feb 2015 14:49:10 +0800 Message-Id: <1423723750-2544-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1423723750-2544-1-git-send-email-greg.bellows@linaro.org> References: <1423723750-2544-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.223.170 Cc: edgar.iglesias@gmail.com, Greg Bellows , a.spyridakis@virtualopensystems.com Subject: [Qemu-devel] [PATCH v7 4/4] target-arm: Add AArch32 guest support to KVM64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add 32-bit to/from 64-bit register synchronization on register gets and puts. Set EL1_32BIT feature flag passed to KVM Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v4 -> v5 - Fix target check v3 -> v4 - Add check that to make sure KVM64 is only being used on AArch64 family of machines. - Relocate register sync to follow register fetches. - Refresh env->aarch64 prior to use. v2 -> v3 - Conditionalize sync of 32-bit and 64-bit registers --- target-arm/kvm64.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 033babf..48fdb87 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -82,7 +82,7 @@ int kvm_arch_init_vcpu(CPUState *cs) ARMCPU *cpu = ARM_CPU(cs); if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || - !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + !object_dynamic_cast(cpu, TYPE_AARCH64_CPU)) { fprintf(stderr, "KVM is not supported for this guest CPU type\n"); return -EINVAL; } @@ -96,6 +96,9 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->psci_version = 2; cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; } + if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; + } /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); @@ -133,6 +136,13 @@ int kvm_arch_put_registers(CPUState *cs, int level) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + /* If we are in AArch32 mode then we need to copy the AArch32 regs to the + * AArch64 registers before pushing them out to 64-bit KVM. + */ + if (!is_a64(env)) { + aarch64_sync_32_to_64(env); + } + for (i = 0; i < 31; i++) { reg.id = AARCH64_CORE_REG(regs.regs[i]); reg.addr = (uintptr_t) &env->xregs[i]; @@ -162,7 +172,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) } /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ - val = pstate_read(env); + if (is_a64(env)) { + val = pstate_read(env); + } else { + val = cpsr_read(env); + } reg.id = AARCH64_CORE_REG(regs.pstate); reg.addr = (uintptr_t) &val; ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); @@ -242,7 +256,14 @@ int kvm_arch_get_registers(CPUState *cs) if (ret) { return ret; } - pstate_write(env, val); + + env->aarch64 = ((val & PSTATE_nRW) == 0); + if (is_a64(env)) { + pstate_write(env, val); + } else { + env->uncached_cpsr = val & CPSR_M; + cpsr_write(env, val, 0xffffffff); + } /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the * QEMU side we keep the current SP in xregs[31] as well. @@ -256,6 +277,15 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } + /* If we are in AArch32 mode then we need to sync the AArch32 regs with the + * incoming AArch64 regs received from 64-bit KVM. + * We must perform this after all of the registers have been acquired from + * the kernel. + */ + if (!is_a64(env)) { + aarch64_sync_64_to_32(env); + } + reg.id = AARCH64_CORE_REG(elr_el1); reg.addr = (uintptr_t) &env->elr_el[1]; ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);