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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id e88si5260253qga.58.2015.02.10.02.51.52 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 10 Feb 2015 02:51:53 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:39034 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YL8Q4-0005Or-7m for patch@linaro.org; Tue, 10 Feb 2015 05:51:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60578) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YL8P4-0004NS-QT for qemu-devel@nongnu.org; Tue, 10 Feb 2015 05:50:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YL8P0-00057k-4l for qemu-devel@nongnu.org; Tue, 10 Feb 2015 05:50:50 -0500 Received: from mail-pd0-f179.google.com ([209.85.192.179]:38750) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YL8Oz-00057g-RF for qemu-devel@nongnu.org; Tue, 10 Feb 2015 05:50:46 -0500 Received: by pdbft15 with SMTP id ft15so38332392pdb.5 for ; Tue, 10 Feb 2015 02:50:45 -0800 (PST) X-Received: by 10.68.203.226 with SMTP id kt2mr36030833pbc.141.1423565445305; Tue, 10 Feb 2015 02:50:45 -0800 (PST) Received: from localhost.localdomain ([210.177.145.249]) by mx.google.com with ESMTPSA id ht2sm7174678pdb.82.2015.02.10.02.50.43 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 10 Feb 2015 02:50:44 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org, alex.bennee@linaro.org, edgar.iglesias@gmail.com Date: Tue, 10 Feb 2015 18:50:14 +0800 Message-Id: <1423565415-5844-4-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1423565415-5844-1-git-send-email-greg.bellows@linaro.org> References: <1423565415-5844-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.179 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v4 3/4] target-arm: Add 32/64-bit register sync X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add AArch32 to AArch64 register sychronization functions. Replace manual register synchronization with new functions in aarch64_cpu_do_interrupt() and HELPER(exception_return)(). Signed-off-by: Greg Bellows --- v3 -> v4 - Rework sync routines to cover various exception levels - Move sync routines to helper.c v2 -> v3 - Conditionalize interrupt handler update of aarch64. --- target-arm/cpu.h | 2 + target-arm/helper-a64.c | 5 +- target-arm/helper.c | 181 ++++++++++++++++++++++++++++++++++++++++++++++++ target-arm/op_helper.c | 6 +- 4 files changed, 186 insertions(+), 8 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1830a12..11845a6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -495,6 +495,8 @@ typedef struct CPUARMState { ARMCPU *cpu_arm_init(const char *cpu_model); int cpu_arm_exec(CPUARMState *s); uint32_t do_arm_semihosting(CPUARMState *env); +void aarch64_sync_32_to_64(CPUARMState *env); +void aarch64_sync_64_to_32(CPUARMState *env); static inline bool is_a64(CPUARMState *env) { diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 8aa40e9..7e0d038 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -466,7 +466,6 @@ void aarch64_cpu_do_interrupt(CPUState *cs) unsigned int new_el = arm_excp_target_el(cs, cs->exception_index); target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); - int i; if (arm_current_el(env) < new_el) { if (env->aarch64) { @@ -530,9 +529,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } env->elr_el[new_el] = env->regs[15]; - for (i = 0; i < 15; i++) { - env->xregs[i] = env->regs[i]; - } + aarch64_sync_32_to_64(env); env->condexec_bits = 0; } diff --git a/target-arm/helper.c b/target-arm/helper.c index 1a1a005..c1d6764 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4096,6 +4096,15 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) return 1; } +void aarch64_sync_64_to_32(CPUARMState *env) +{ + int i; + + for (i = 0; i < 15; i++) { + env->regs[i] = env->xregs[i]; + } +} + #else /* Map CPU modes onto saved register banks. */ @@ -4425,6 +4434,178 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) env->thumb = addr & 1; } +/* Function used to synchronize QEMU's AArch64 register set with AArch32 + * register set. This is necessary when switching between AArch32 and AArch64 + * execution state. + */ +void aarch64_sync_32_to_64(CPUARMState *env) +{ + int i; + uint32_t mode = env->uncached_cpsr & CPSR_M; + + /* We can blanket copy R[0:7] to X[0:7] */ + for (i = 0; i < 8; i++) { + env->xregs[i] = env->regs[i]; + } + + /* The latest copy of some registers depend on the current executing mode. + * The general purpose copy is used when the current mode corresponds to + * the mapping for the given register. Otherwise, the banked copy + * corresponding to the register mapping is used. + */ + if (mode == ARM_CPU_MODE_USR) { + for (i = 8; i < 15; i++) { + env->xregs[i] = env->regs[i]; + } + } else { + for (i = 8; i < 13; i++) { + env->xregs[i] = env->usr_regs[i - 8]; + } + env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; + env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; + } + + if (mode == ARM_CPU_MODE_HYP) { + env->xregs[15] = env->regs[13]; + } else { + env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; + } + + if (mode == ARM_CPU_MODE_IRQ) { + env->xregs[16] = env->regs[13]; + env->xregs[17] = env->regs[14]; + } else { + env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; + env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; + } + + if (mode == ARM_CPU_MODE_SVC) { + env->xregs[18] = env->regs[13]; + env->xregs[19] = env->regs[14]; + } else { + env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; + env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; + } + + if (mode == ARM_CPU_MODE_ABT) { + env->xregs[20] = env->regs[13]; + env->xregs[21] = env->regs[14]; + } else { + env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; + env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; + } + + if (mode == ARM_CPU_MODE_UND) { + env->xregs[22] = env->regs[13]; + env->xregs[23] = env->regs[14]; + } else { + env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; + env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; + } + + if (mode == ARM_CPU_MODE_FIQ) { + for (i = 24; i < 31; i++) { + env->xregs[i] = env->regs[i - 16]; /* X[24:30] -> R[8:14] */ + } + } else { + for (i = 24; i < 29; i++) { + env->xregs[i] = env->fiq_regs[i - 24]; + } + env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; + env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; + } + + env->pc = env->regs[15]; +} + +/* Function used to synchronize QEMU's AArch32 register set with AArch64 + * register set. This is necessary when switching between AArch32 and AArch64 + * execution state. + */ +void aarch64_sync_64_to_32(CPUARMState *env) +{ + int i; + uint32_t mode = env->uncached_cpsr & CPSR_M; + + /* We can blanket copy X[0:7] to R[0:7] */ + for (i = 0; i < 8; i++) { + env->regs[i] = env->xregs[i]; + } + + /* The destination of some registers depend on the current executing mode. + * The AArch32 registers 8-12 are only sync'd when we are in USR or FIQ + * mode as they are the only modes where AArch64 registers map to these + * registers. In all other cases, the respective USR and FIQ banks are + * sync'd. + * The AArch32 registers 13 & 14 are sync'd depending on the execution mode + * we are in. If we are not in a given mode, the bank corresponding to the + * AArch64 register is sync'd. + */ + if (mode == ARM_CPU_MODE_USR) { + for (i = 8; i < 15; i++) { + env->regs[i] = env->xregs[i]; + } + } else { + for (i = 8; i < 13; i++) { + env->usr_regs[i - 8] = env->xregs[i]; + } + env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; + env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; + } + + if (mode == ARM_CPU_MODE_HYP) { + env->regs[13] = env->xregs[15]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; + } + + if (mode == ARM_CPU_MODE_IRQ) { + env->regs[13] = env->xregs[16]; + env->regs[14] = env->xregs[17]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; + env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; + } + + if (mode == ARM_CPU_MODE_SVC) { + env->regs[13] = env->xregs[18]; + env->regs[14] = env->xregs[19]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; + env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; + } + + if (mode == ARM_CPU_MODE_ABT) { + env->regs[13] = env->xregs[20]; + env->regs[14] = env->xregs[21]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; + env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; + } + + if (mode == ARM_CPU_MODE_UND) { + env->regs[13] = env->xregs[22]; + env->regs[14] = env->xregs[23]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; + env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; + } + + if (mode == ARM_CPU_MODE_FIQ) { + for (i = 8; i < 15; i++) { + env->regs[i] = env->xregs[i + 16]; /* X[24:30] -> R[8:14] */ + } + } else { + for (i = 0; i < 5; i++) { + env->fiq_regs[i] = env->xregs[i + 24]; + } + env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; + env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; + } + + env->regs[15] = env->pc; +} + /* Handle a CPU exception. */ void arm_cpu_do_interrupt(CPUState *cs) { diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 2bed914..7713022 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -465,7 +465,7 @@ void HELPER(exception_return)(CPUARMState *env) int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); uint32_t spsr = env->banked_spsr[spsr_idx]; - int new_el, i; + int new_el; aarch64_save_sp(env, cur_el); @@ -491,9 +491,7 @@ void HELPER(exception_return)(CPUARMState *env) if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS; } - for (i = 0; i < 15; i++) { - env->regs[i] = env->xregs[i]; - } + aarch64_sync_64_to_32(env); env->regs[15] = env->elr_el[1] & ~0x1; } else {