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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id g2si17942448qch.1.2015.02.10.02.53.11 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 10 Feb 2015 02:53:12 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:39044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YL8RL-0007fS-M4 for patch@linaro.org; Tue, 10 Feb 2015 05:53:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60556) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YL8P0-0004IZ-Bx for qemu-devel@nongnu.org; Tue, 10 Feb 2015 05:50:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YL8Ov-00056y-BC for qemu-devel@nongnu.org; Tue, 10 Feb 2015 05:50:46 -0500 Received: from mail-pd0-f182.google.com ([209.85.192.182]:40221) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YL8Ou-00056q-Um for qemu-devel@nongnu.org; Tue, 10 Feb 2015 05:50:41 -0500 Received: by pdev10 with SMTP id v10so20950373pde.7 for ; Tue, 10 Feb 2015 02:50:40 -0800 (PST) X-Received: by 10.68.162.130 with SMTP id ya2mr36227854pbb.113.1423565440404; Tue, 10 Feb 2015 02:50:40 -0800 (PST) Received: from localhost.localdomain ([210.177.145.249]) by mx.google.com with ESMTPSA id ht2sm7174678pdb.82.2015.02.10.02.50.38 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 10 Feb 2015 02:50:39 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org, alex.bennee@linaro.org, edgar.iglesias@gmail.com Date: Tue, 10 Feb 2015 18:50:12 +0800 Message-Id: <1423565415-5844-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1423565415-5844-1-git-send-email-greg.bellows@linaro.org> References: <1423565415-5844-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.182 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v4 1/4] target-arm: Add CPU property to disable AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.49 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Adds registration and get/set functions for enabling/disabling the AArch64 execution state on AArch64 CPUs. By default AArch64 execution state is enabled on AArch64 CPUs, setting the property to off, will disable the execution state. The below QEMU invocation would have AArch64 execution state disabled. $ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off Also adds stripping of features from CPU model string in acquiring the ARM CPU by name. Signed-off-by: Greg Bellows --- v3 -> v4 - Switch from using strtok to g_strsplit - Add disablement of aarch64 option if KVM is not enabled. v1 -> v2 - Scrap the custom CPU feature parsing in favor of using the default CPU parsing. - Add registration of CPU AArch64 property to disable/enable the AArch64 feature. --- target-arm/cpu.c | 5 ++++- target-arm/cpu64.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d38af74..986f04c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -544,13 +544,16 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; char *typename; + char **cpuname; if (!cpu_model) { return NULL; } - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); + cpuname = g_strsplit(cpu_model, ",", 1); + typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); oc = object_class_by_name(typename); + g_strfreev(cpuname); g_free(typename); if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || object_class_is_abstract(oc)) { diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bb778b3..d03f203 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -32,6 +32,11 @@ static inline void set_feature(CPUARMState *env, int feature) env->features |= 1ULL << feature; } +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &= ~(1ULL << feature); +} + #ifndef CONFIG_USER_ONLY static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -170,8 +175,42 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = NULL } }; +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + /* At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes a + * uniform execution state like do_interrupt. + */ + if (!kvm_enabled()) { + error_setg(errp, + "'aarch64' option only supported with '-enable-kvm'"); + return; + } + + if (value == false) { + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + static void aarch64_cpu_initfn(Object *obj) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64, NULL); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarch64 " + "execution state ", + NULL); } static void aarch64_cpu_finalizefn(Object *obj)