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[67.52.129.61]) by mx.google.com with ESMTPSA id bq7sm9972513pdb.50.2014.12.15.10.51.45 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 15 Dec 2014 10:51:46 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 15 Dec 2014 12:51:15 -0600 Message-Id: <1418669479-23908-12-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1418669479-23908-1-git-send-email-greg.bellows@linaro.org> References: <1418669479-23908-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.54 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v3 11/15] target-arm: Enable CPU has_el3 prop during VE init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Adds setting of the CPU has_el3 property based on the vexpress machine secure state property during initialization. This enables/disables EL3 state during start-up. Changes include adding an additional secure state boolean during vexpress CPU initialization. Also enables the ARM secure boot by default. Signed-off-by: Greg Bellows --- v1 -> v2 - Changes CPU property name from "secure" to "has_el3" - Change conditional to handle machine state default of secure. The check now checks if the machine secure property has been disabled which causes the CPU EL3 feautre to be disabled. - Add setting of arm_boot_info.secure_boot to true v2 -> v3 - Silently ignore error if "has_el3" does not exist. - Revise secure machine property description --- hw/arm/vexpress.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index c82c32e..19d1f00 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -167,6 +167,9 @@ typedef struct { bool secure; } VexpressMachineState; +#define SECURE_PROP_DESC \ + "Set on/off to enable/disable the ARM Security Extensions (TrustZone)" + #define TYPE_VEXPRESS_MACHINE "vexpress" #define TYPE_VEXPRESS_A9_MACHINE "vexpress-a9" #define TYPE_VEXPRESS_A15_MACHINE "vexpress-a15" @@ -196,7 +199,7 @@ struct VEDBoardInfo { }; static void init_cpus(const char *cpu_model, const char *privdev, - hwaddr periphbase, qemu_irq *pic) + hwaddr periphbase, qemu_irq *pic, bool secure) { ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); DeviceState *dev; @@ -213,6 +216,10 @@ static void init_cpus(const char *cpu_model, const char *privdev, Object *cpuobj = object_new(object_class_get_name(cpu_oc)); Error *err = NULL; + if (!secure) { + object_property_set_bool(cpuobj, false, "has_el3", &err); + } + if (object_property_find(cpuobj, "reset-cbar", NULL)) { object_property_set_int(cpuobj, periphbase, "reset-cbar", &error_abort); @@ -288,7 +295,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x60000000, ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ - init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); + init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure); /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ @@ -374,7 +381,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x80000000, ram); /* 0x2c000000 A15MPCore private memory region (GIC) */ - init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); + init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure); /* A15 daughterboard peripherals: */ @@ -699,6 +706,8 @@ static void vexpress_common_init(MachineState *machine) daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; + /* Indicate that when booting Linux we should be in secure state */ + daughterboard->bootinfo.secure_boot = true; arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); } @@ -724,9 +733,7 @@ static void vexpress_instance_init(Object *obj) vms->secure = true; object_property_add_bool(obj, "secure", vexpress_get_secure, vexpress_set_secure, NULL); - object_property_set_description(obj, "secure", - "Set on/off to enable/disable secure state", - NULL); + object_property_set_description(obj, "secure", SECURE_PROP_DESC, NULL); } static void vexpress_class_init(ObjectClass *oc, void *data)