From patchwork Thu Nov 6 15:51:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40352 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f70.google.com (mail-ee0-f70.google.com [74.125.83.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E897C20C4E for ; Thu, 6 Nov 2014 16:07:51 +0000 (UTC) Received: by mail-ee0-f70.google.com with SMTP id b57sf2353100eek.1 for ; Thu, 06 Nov 2014 08:07:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=zT7PNR0Jrab0A/rswcx8hzoQA05IebrK8wmErzc+o/k=; b=VKkHXYr1jmGBZvt4u5ihqZmbFxIHSWuGfLPjU0yoDulkUMuxgQjtHoWo6YPiCHYZ34 ES/mPz1qeatf15qyO7c8b+Une/1iv2YZY8z8YEVO+/5vz09gFkSslwz67bstNTT8NXNo 6BHpO+zvxr3lcC9J+lcDtKloPALUMeDaWBgNRX+0Uac8pyIzZbwFk9vNTSxaZHJEoCjY VX04Izau/N+0zmW2bWYRGa8pqPF5wE4PBqfPCoXqoeD+hvcwCXIG0+e9g6ta1CM2YGtU Jcm+3m/75oFLK17BVHX3SYZEItZGwEDgh+47S/OHu5EHPXoll0tAO8GHLUuNSqVPtqIT dgbg== X-Gm-Message-State: ALoCoQkHj/9leeq5M88USB1fyOv1L9/R5PI9pfETzGVaG4AW2zXRdQJwW7KSF2LPASM/EihapfoY X-Received: by 10.112.163.229 with SMTP id yl5mr40876lbb.23.1415290071172; Thu, 06 Nov 2014 08:07:51 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.243.4 with SMTP id wu4ls105292lac.51.gmail; Thu, 06 Nov 2014 08:07:50 -0800 (PST) X-Received: by 10.112.57.227 with SMTP id l3mr5877086lbq.68.1415290070920; Thu, 06 Nov 2014 08:07:50 -0800 (PST) Received: from mail-la0-f42.google.com (mail-la0-f42.google.com. [209.85.215.42]) by mx.google.com with ESMTPS id j10si11846920laf.95.2014.11.06.08.07.50 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 08:07:50 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) client-ip=209.85.215.42; Received: by mail-la0-f42.google.com with SMTP id gq15so2899787lab.29 for ; Thu, 06 Nov 2014 08:07:50 -0800 (PST) X-Received: by 10.112.202.104 with SMTP id kh8mr5977624lbc.46.1415290070780; Thu, 06 Nov 2014 08:07:50 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp67680lbc; Thu, 6 Nov 2014 08:07:49 -0800 (PST) X-Received: by 10.140.93.195 with SMTP id d61mr7834965qge.28.1415290068777; Thu, 06 Nov 2014 08:07:48 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id c1si12375616qam.98.2014.11.06.08.07.48 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 06 Nov 2014 08:07:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:54696 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPb9-00029I-NB for patch@linaro.org; Thu, 06 Nov 2014 11:07:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPMA-0002bm-Kr for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPM5-0004Qi-Cj for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:18 -0500 Received: from mail-pa0-f52.google.com ([209.85.220.52]:63975) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPM5-0004Qc-82 for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:13 -0500 Received: by mail-pa0-f52.google.com with SMTP id fa1so1496659pad.11 for ; Thu, 06 Nov 2014 07:52:12 -0800 (PST) X-Received: by 10.66.248.104 with SMTP id yl8mr5460670pac.2.1415289132621; Thu, 06 Nov 2014 07:52:12 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.52.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:52:11 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:51:10 -0600 Message-Id: <1415289073-14681-24-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.52 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 23/26] target-arm: make VBAR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Revert unnecessary CPreg definition changes v5 -> v6 - Changed _el field variants to be array based - Merged VBAR and VBAR_EL1 reginfo entries v3 -> v4 - Fix vbar union/structure definition - Revert back to array-based vbar definition combined with v7 naming --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 5 +++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4ddfe77..0bf88a2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -297,7 +297,15 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t vbar_el[4]; /* vector base address register */ + union { /* vector base address register */ + struct { + uint64_t _unused_vbar; + uint64_t vbar_ns; + uint64_t hvbar; + uint64_t vbar_s; + }; + uint64_t vbar_el[4]; + }; uint32_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 67cb649..d4461f0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -911,7 +911,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, - .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), + offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue = 0 }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, @@ -4402,7 +4403,7 @@ void arm_cpu_do_interrupt(CPUState *cs) * This register is only followed in non-monitor mode, and is banked. * Note: only bits 31:5 are valid. */ - addr += env->cp15.vbar_el[1]; + addr += A32_BANKED_CURRENT_REG_GET(env, vbar); } if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {