From patchwork Wed Nov 5 23:23:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 40243 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f200.google.com (mail-lb0-f200.google.com [209.85.217.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9E46E240A6 for ; Wed, 5 Nov 2014 23:35:16 +0000 (UTC) Received: by mail-lb0-f200.google.com with SMTP id f15sf1098127lbj.11 for ; Wed, 05 Nov 2014 15:35:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=Jstc2FpVi85zOZJXILIcwHqAeYLGZKjFjnC3D+grJJo=; b=HZzgfSgmJ4CNFHgXXDee6q6JK+cpr6X8Zht93FdrUI8Kz2QS/9lJICwcNJgL7Btslt 9S/EZ0ntxEs9oLyAwMcBIxpikBjxQZ36LmPT0Ic9I8WENTFoMQsLeMox4u0uXdA5FaCW /fEYlPkETlfuv/VEALvvBuA3kZQQNceBqL6NTqHU3gb1rEwfneGbe74natbjwlwzXlMA tLkwUOIE2hdkVmWnG0VB3g/hbonHtMphSbAyjuDYq0cDoAIPsBFyx2SYGemi12Dd8pRs cNQWrj++NzPAJVN+QI/TATuCGRw0spwBoboh2CVQiqW2vblAgbZ0BpuiNCnGnH6Gwt96 45FA== X-Gm-Message-State: ALoCoQlX0qTt+SIHoqWuFzTJWT72N/ryph5G/Bjs7UWQk2AQV26yGOOGvudkTvSeG3+5VNqdRrg8 X-Received: by 10.112.48.98 with SMTP id k2mr18599lbn.15.1415230515211; Wed, 05 Nov 2014 15:35:15 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.10.2 with SMTP id e2ls7513lab.88.gmail; Wed, 05 Nov 2014 15:35:14 -0800 (PST) X-Received: by 10.152.21.199 with SMTP id x7mr645548lae.66.1415230514939; Wed, 05 Nov 2014 15:35:14 -0800 (PST) Received: from mail-lb0-f174.google.com (mail-lb0-f174.google.com. [209.85.217.174]) by mx.google.com with ESMTPS id sd7si8785004lbb.51.2014.11.05.15.35.14 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:35:14 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) client-ip=209.85.217.174; Received: by mail-lb0-f174.google.com with SMTP id p9so1543645lbv.5 for ; Wed, 05 Nov 2014 15:35:14 -0800 (PST) X-Received: by 10.112.52.37 with SMTP id q5mr698282lbo.32.1415230514417; Wed, 05 Nov 2014 15:35:14 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp372331lbc; Wed, 5 Nov 2014 15:35:13 -0800 (PST) X-Received: by 10.229.118.1 with SMTP id t1mr1092342qcq.17.1415230513144; Wed, 05 Nov 2014 15:35:13 -0800 (PST) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f67si9002669qgf.83.2014.11.05.15.35.12 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:35:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:49058 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmA6a-0007dr-3D for patch@linaro.org; Wed, 05 Nov 2014 18:35:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56466) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vc-0004Vh-Cu for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xm9vX-0004fh-3C for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:52 -0500 Received: from mail-pd0-f173.google.com ([209.85.192.173]:56108) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xm9vW-0004fb-Q7 for qemu-devel@nongnu.org; Wed, 05 Nov 2014 18:23:46 -0500 Received: by mail-pd0-f173.google.com with SMTP id v10so1680871pde.18 for ; Wed, 05 Nov 2014 15:23:46 -0800 (PST) X-Received: by 10.68.231.232 with SMTP id tj8mr417996pbc.166.1415229826080; Wed, 05 Nov 2014 15:23:46 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r4sm4086349pdm.93.2014.11.05.15.23.44 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Nov 2014 15:23:45 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Wed, 5 Nov 2014 17:23:03 -0600 Message-Id: <1415229793-3278-17-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> References: <1415229793-3278-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.173 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v9 16/26] target-arm: make TTBR0/1 banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v8 -> v9 - Fixed naming of TTBR0/1 and defined with opc0 instead of cp - Removed get_phys_addr_lpae() AArch64 EL3 support. - Remove stray whitespace change in pxa2xx.c v5 -> v6 - Changed _el field variants to be array based - Merged TTBR# and TTBR#_EL1 reginfo entries - Globally replace Aarch# with AArch# --- hw/arm/pxa2xx.c | 2 +- target-arm/cpu.h | 20 ++++++++++++++++++-- target-arm/helper.c | 37 +++++++++++++++++++++++++------------ 3 files changed, 44 insertions(+), 15 deletions(-) diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 11d51af..2b00b59 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -275,7 +275,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; s->cpu->env.cp15.sctlr_ns = 0; s->cpu->env.cp15.c1_coproc = 0; - s->cpu->env.cp15.ttbr0_el1 = 0; + s->cpu->env.cp15.ttbr0_el[1] = 0; s->cpu->env.cp15.c3 = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6996f7c..df761b4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -199,8 +199,24 @@ typedef struct CPUARMState { uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ - uint64_t ttbr0_el1; /* MMU translation table base 0. */ - uint64_t ttbr1_el1; /* MMU translation table base 1. */ + union { /* MMU translation table base 0. */ + struct { + uint64_t _unused_ttbr0_0; + uint64_t ttbr0_ns; + uint64_t _unused_ttbr0_1; + uint64_t ttbr0_s; + }; + uint64_t ttbr0_el[4]; + }; + union { /* MMU translation table base 1. */ + struct { + uint64_t _unused_ttbr1_0; + uint64_t ttbr1_ns; + uint64_t _unused_ttbr1_1; + uint64_t ttbr1_s; + }; + uint64_t ttbr1_el[4]; + }; uint64_t c2_control; /* MMU translation table base control. */ uint32_t c2_mask; /* MMU translation table base selection mask. */ uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 6f48291..1e478a1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1646,13 +1646,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), - .writefn = vmsa_ttbr_write, .resetvalue = 0 }, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, + .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), + offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), - .writefn = vmsa_ttbr_write, .resetvalue = 0 }, + .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, + .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), + offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .writefn = vmsa_tcr_el1_write, @@ -1883,11 +1885,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 }, { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, - .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), + offsetof(CPUARMState, cp15.ttbr0_ns) }, .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, - .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), + offsetof(CPUARMState, cp15.ttbr1_ns) }, .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore }, REGINFO_SENTINEL }; @@ -2341,6 +2345,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write, .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) }, + { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, + .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, @@ -4443,18 +4451,23 @@ static inline int check_ap(CPUARMState *env, int ap, int domain_prot, static bool get_level1_table_address(CPUARMState *env, uint32_t *table, uint32_t address) { + /* We only get here if EL1 is running in AArch32. If EL3 is running in + * AArch32 there is a secure and non-secure instance of the translation + * table registers. + */ if (address & env->cp15.c2_mask) { if ((env->cp15.c2_control & TTBCR_PD1)) { /* Translation table walk disabled for TTBR1 */ return false; } - *table = env->cp15.ttbr1_el1 & 0xffffc000; + *table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000; } else { if ((env->cp15.c2_control & TTBCR_PD0)) { /* Translation table walk disabled for TTBR0 */ return false; } - *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask; + *table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & + env->cp15.c2_base_mask; } *table |= (address >> 18) & 0x3ffc; return true; @@ -4759,7 +4772,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, * we will always flush the TLB any time the ASID is changed). */ if (ttbr_select == 0) { - ttbr = env->cp15.ttbr0_el1; + ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0); epd = extract32(env->cp15.c2_control, 7, 1); tsz = t0sz; @@ -4771,7 +4784,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, granule_sz = 11; } } else { - ttbr = env->cp15.ttbr1_el1; + ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1); epd = extract32(env->cp15.c2_control, 23, 1); tsz = t1sz;