From patchwork Thu Oct 30 21:28:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 39965 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f197.google.com (mail-wi0-f197.google.com [209.85.212.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 72AA42405B for ; Fri, 31 Oct 2014 19:01:01 +0000 (UTC) Received: by mail-wi0-f197.google.com with SMTP id ex7sf981215wid.8 for ; Fri, 31 Oct 2014 12:01:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=shhnnCemJGlWrmUFBLy3rx5oHd7QlGVVhziwqozb34Y=; b=TZWng1B2WblrmtByDowunAfovvuFhsLo2YRn7aRWkU7dHQjh92Fm15OnmaTqA43rKr RFPhmn1ojUR5rYv+EOo+acMx4QjwmfsGCnSnAXNrYBjqIWHo0c4mSJ9YkJ/4fjs4BN+J 7cKcn8oscyykRxXT87ERYrsHfA85dY3txGiUslmk7z8xPVOjLCmAfczp9OMnY4Mu8z9I /BVHyVz8YXDKixqh/NoTy5rfG5TvC/zsJi4EvjivHEC4DKgJSqGLKUuOJkEFk3rAkpjj G4BBSKnwycM2Osz7ALuTTAvGcLhC+WINuKx7M6mNi+t7K4NGkazhYBxesR1LJIZ4zt6p 7Mog== X-Gm-Message-State: ALoCoQlT9mQv0mk/EtVGcpxf1R/sWC12YYSSaW902HlLsQIYxlyI/+MV+5w5TTzT5PNp8Dn9TN55 X-Received: by 10.194.91.208 with SMTP id cg16mr7422wjb.5.1414782060650; Fri, 31 Oct 2014 12:01:00 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.7.137 with SMTP id j9ls279261laa.45.gmail; Fri, 31 Oct 2014 12:00:59 -0700 (PDT) X-Received: by 10.112.73.103 with SMTP id k7mr28622880lbv.41.1414782059865; Fri, 31 Oct 2014 12:00:59 -0700 (PDT) Received: from mail-la0-f48.google.com (mail-la0-f48.google.com. [209.85.215.48]) by mx.google.com with ESMTPS id f6si18317917lbc.6.2014.10.31.12.00.59 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 12:00:59 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) client-ip=209.85.215.48; Received: by mail-la0-f48.google.com with SMTP id gq15so6606241lab.7 for ; Fri, 31 Oct 2014 12:00:59 -0700 (PDT) X-Received: by 10.112.130.41 with SMTP id ob9mr28034207lbb.74.1414782059727; Fri, 31 Oct 2014 12:00:59 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.84.229 with SMTP id c5csp246847lbz; Fri, 31 Oct 2014 12:00:58 -0700 (PDT) X-Received: by 10.224.32.65 with SMTP id b1mr40176231qad.30.1414782058234; Fri, 31 Oct 2014 12:00:58 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a1si18507435qae.56.2014.10.31.12.00.57 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 31 Oct 2014 12:00:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:41312 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkHRR-0002Ya-Dp for patch@linaro.org; Fri, 31 Oct 2014 15:00:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52716) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkE68-0001z8-AF for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:27:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjxHQ-0004fw-Em for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:21 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:50515) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjxHQ-0004eq-6X for qemu-devel@nongnu.org; Thu, 30 Oct 2014 17:29:16 -0400 Received: by mail-pa0-f51.google.com with SMTP id kq14so6287481pab.38 for ; Thu, 30 Oct 2014 14:29:15 -0700 (PDT) X-Received: by 10.70.11.2 with SMTP id m2mr20256385pdb.31.1414704555501; Thu, 30 Oct 2014 14:29:15 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id o5sm8017713pdr.50.2014.10.30.14.29.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 14:29:14 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Thu, 30 Oct 2014 16:28:36 -0500 Message-Id: <1414704538-17103-6-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> References: <1414704538-17103-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.51 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v8 05/27] target-arm: add CPREG secure state support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v7 -> v8 - Break up the fieldoffset union to avoid need for sometimes overwriting one bank when updating fieldoffset. This also removes the need for the #define short-cut introduced in v7. v6 -> v7 - Add naming for fieldoffset fields and macros for accessing. This was needed to overcome issues with the GCC-4.4 compiler. v5 -> v6 - Separate out secure CPREG flags - Add convenience macro for testing flags - Removed extraneous newline - Move add_cpreg_to_hashtable() functionality to a later commit for which it is dependent on. - Added comment explaining fieldoffset padding v4 -> v5 - Added ARM CP register secure and non-secure bank flags - Added setting of secure and non-secure flags furing registration --- target-arm/cpu.h | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ba621fa..51117fb 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -993,6 +993,24 @@ enum { ARM_CP_STATE_BOTH = 2, }; +/* ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates that + * the register has both a secure and non-secure hash entry. A single one of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is secure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ +}; + +/* Convenience macro for checking for a specific bit */ +#define ARM_CP_SECSTATE_TEST(_ri, _flag) (((_ri)->secure & (_flag)) == (_flag)) + /* Return true if cptype is a valid type field. This is used to try to * catch errors where the sentinel has been accidentally left off the end * of a list of registers. @@ -1127,6 +1145,8 @@ struct ARMCPRegInfo { int type; /* Access rights: PL*_[RW] */ int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the * register read/write functions, since they are passed the ARMCPRegInfo*. @@ -1136,12 +1156,27 @@ struct ARMCPRegInfo { * fieldoffset is non-zero, the reset value of the register. */ uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. This is not - * needed if either: + /* Offset of the field in CPUARMState for this register. + * + * This is not needed if either: * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs * 2. both readfn and writefn are specified */ - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + ptrdiff_t fieldoffset; + + /* Offsets of the secure and non-secure fields in CPUARMState for the + * register if it is banked. These fields are only used during the static + * registration of a register. During hashing the bank associated + * with a given security state is copied to fieldoffset which is used from + * there on out. + * + * It is expected that register definitions use either fieldoffset or + * bank_fieldoffsets in the definition but not both. It is also expected + * that both bank offsets are set when defining a banked register. This + * use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + /* Function for making any access checks for this register in addition to * those specified by the 'access' permissions bits. If NULL, no extra * checks required. The access check is performed at runtime, not at