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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id c90si786660qgf.111.2014.10.27.23.39.29 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 27 Oct 2014 23:39:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:37368 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xj0RF-0004xU-L5 for patch@linaro.org; Tue, 28 Oct 2014 02:39:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xj0Qk-0004fs-1N for qemu-devel@nongnu.org; Tue, 28 Oct 2014 02:39:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xj0Qe-0007RE-DR for qemu-devel@nongnu.org; Tue, 28 Oct 2014 02:38:57 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:46065) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xj0Qe-0007R1-7G for qemu-devel@nongnu.org; Tue, 28 Oct 2014 02:38:52 -0400 Received: by mail-pa0-f51.google.com with SMTP id kq14so22276pab.38 for ; Mon, 27 Oct 2014 23:38:50 -0700 (PDT) X-Received: by 10.67.15.69 with SMTP id fm5mr1195951pad.91.1414478330871; Mon, 27 Oct 2014 23:38:50 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id jt1sm670420pbc.3.2014.10.27.23.38.47 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 27 Oct 2014 23:38:50 -0700 (PDT) From: Pranavkumar Sawargaonkar To: qemu-devel@nongnu.org Date: Tue, 28 Oct 2014 12:08:01 +0530 Message-Id: <1414478281-5956-1-git-send-email-pranavkumar@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.51 Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, patches@apm.com, Pranavkumar Sawargaonkar , alex.bennee@linaro.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH] target-arm: Add guest cpu endianness determination for virtio in KVM ARM64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pranavkumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patch implements a fucntion pointer virtio_is_big_endian() from "CPUClass" structure for arm64. Function aarch64_cpu_virtio_endianness() is added to determine and returns the guest cpu endianness to virtio. This is required for running cross endian guests with virtio on ARM64. Signed-off-by: Pranavkumar Sawargaonkar --- include/hw/virtio/virtio-access.h | 2 ++ target-arm/cpu64.c | 41 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-access.h index 46456fd..84fa701 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -23,6 +23,8 @@ static inline bool virtio_access_is_big_endian(VirtIODevice *vdev) return virtio_is_big_endian(vdev); #elif defined(TARGET_WORDS_BIGENDIAN) return true; +#elif defined(TARGET_AARCH64) + return virtio_is_big_endian(vdev); #else return false; #endif diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index c30f47e..789f886 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -192,6 +192,43 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) } } +#ifndef CONFIG_USER_ONLY + +#define KVM_REG_ARM64_SCTLR_EL1 3, 0, 1, 0, 0 + +static bool aarch64_cpu_virtio_endianness(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + struct kvm_one_reg reg; + uint64_t sctlr; + + cpu_synchronize_state(cs); + + /* Check if we are running 32bit guest or not */ + if (!is_a64(env)) + return (env->pstate & CPSR_E) ? 1 : 0; + + /* Ideally we do not need to call IOCTL again to read SCTLR_EL1 value. + * cpu_synchronize_state() should fill the env->cp15.c1_sys + * to get this value but this path is currently not implemented for arm64. + * Hence this is a temporary fix. + */ + + reg.id = ARM64_SYS_REG(KVM_REG_ARM64_SCTLR_EL1); + reg.addr = (uint64_t) &sctlr; + kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + + if ((env->pstate & 0xf) == PSTATE_MODE_EL0t) + sctlr &= (1U <<24); + else + sctlr &= (1U <<25); + + /* If BIG-ENDIAN return 1 */ + return sctlr ? 1 : 0; +} +#endif + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -203,6 +240,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34; cc->gdb_core_xml_file = "aarch64-core.xml"; +#ifndef CONFIG_USER_ONLY + cc->virtio_is_big_endian = aarch64_cpu_virtio_endianness; +#endif + } static void aarch64_cpu_register(const ARMCPUInfo *info)