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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id ej1si13381571wib.72.2014.10.21.09.59.40 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:59:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52425 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcmZ-0003Id-5q for patch@linaro.org; Tue, 21 Oct 2014 12:59:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42017) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj9-0006iu-SP for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj3-0006pa-3n for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:07 -0400 Received: from mail-qg0-f50.google.com ([209.85.192.50]:49920) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj2-0006pQ-Vo for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:01 -0400 Received: by mail-qg0-f50.google.com with SMTP id q108so1158391qgd.23 for ; Tue, 21 Oct 2014 09:56:00 -0700 (PDT) X-Received: by 10.140.28.10 with SMTP id 10mr45282075qgy.15.1413910559377; Tue, 21 Oct 2014 09:55:59 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.55.58 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:55:58 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:20 -0500 Message-Id: <1413910544-20150-9-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.50 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 08/32] target-arm: add async excp target_el function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.46 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Adds a dedicated function for IRQ and FIQ exceptions to determine target_el and mode (AArch32) according to tables in ARM ARMv8 and ARM ARM v7. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Removed unneeded arm_phys_excp_target_el() function prototype. - Removed unneeded arm_phys_excp_target_el() USER_ONLY function. - Fixed up arm_phys_excp_target_el() function definition to be static. - Globally replace Aarch# with AArch# v4 -> v5 - Simplify target EL function including removal of mode which was unused - Merged with patch that plugs in the use of the function v3 -> v4 - Fixed arm_phys_excp_target_el() 0/0/0 case to return excp_mode when EL<2 rather than ABORT. Signed-off-by: Greg Bellows --- target-arm/helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 77 insertions(+), 20 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 38d9f7b..78aeb31 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3762,6 +3762,80 @@ void switch_mode(CPUARMState *env, int mode) } /* + * Determine the target EL for physical exceptions + */ +static inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, + uint32_t cur_el, bool secure) +{ + CPUARMState *env = cs->env_ptr; + uint32_t target_el = 1; + + /* There is no SCR or HCR routing unless the respective EL3 and EL2 + * extensions are supported. This initial setting affects whether any + * other conditions matter. + */ + bool scr_routing = arm_feature(env, ARM_FEATURE_EL3); /* IRQ, FIQ, EA */ + bool hcr_routing = arm_feature(env, ARM_FEATURE_EL2); /* IMO, FMO, AMO */ + + /* Fast-path if EL2 and EL3 are not enabled */ + if (!scr_routing && !hcr_routing) { + return target_el; + } + + switch (excp_idx) { + case EXCP_IRQ: + scr_routing &= ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); + hcr_routing &= ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); + break; + case EXCP_FIQ: + scr_routing &= ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); + hcr_routing &= ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); + } + + /* If SCR routing is enabled we always go to EL3 regardless of EL3 + * execution state + */ + if (scr_routing) { + /* IRQ|FIQ|EA == 1 */ + return 3; + } + + /* If HCR.TGE is set all exceptions that would be routed to EL1 are + * routed to EL2 (in non-secure world). + */ + hcr_routing &= (env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE; + + /* Determine target EL according to ARM ARMv8 tables G1-15 and G1-16 */ + if (arm_el_is_aa64(env, 3)) { + /* EL3 in AArch64 */ + if (!secure) { + /* If non-secure, we may route to EL2 depending on other state. + * If we are coming from the secure world then we always route to + * EL1. + */ + if (hcr_routing || + (cur_el == 2 && !(env->cp15.scr_el3 & SCR_RW))) { + /* If HCR.FMO/IMO is set or we already in EL2 and it is not + * configured to be AArch64 then route to EL2. + */ + target_el = 2; + } + } + } else { + /* EL3 in AArch32 */ + if (secure) { + /* If coming from secure always route to EL3 */ + target_el = 3; + } else if (hcr_routing || cur_el == 2) { + /* If HCR.FMO/IMO is set or we are already EL2 then route to EL2 */ + target_el = 2; + } + } + + return target_el; +} + +/* * Determine the target EL for a given exception type. */ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) @@ -3769,14 +3843,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; unsigned int cur_el = arm_current_el(env); - unsigned int target_el; - /* FIXME: Use actual secure state. */ - bool secure = false; - - if (!env->aarch64) { - /* TODO: Add EL2 and 3 exception handling for AArch32. */ - return 1; - } + unsigned int target_el = 1; + bool secure = arm_is_secure(env); switch (excp_idx) { case EXCP_HVC: @@ -3788,19 +3856,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) break; case EXCP_FIQ: case EXCP_IRQ: - { - const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; - const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; - - target_el = 1; - if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { - target_el = 2; - } - if (env->cp15.scr_el3 & scr_mask) { - target_el = 3; - } + target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); break; - } case EXCP_VIRQ: case EXCP_VFIQ: target_el = 1;