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[208.118.235.17]) by mx.google.com with ESMTPS id h6si23469900qcu.16.2014.10.21.10.00.04 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:00:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:52430 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcmw-0003uA-Mm for patch@linaro.org; Tue, 21 Oct 2014 13:00:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj9-0006iT-GQ for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj1-0006oV-4X for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:07 -0400 Received: from mail-qg0-f48.google.com ([209.85.192.48]:42124) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj1-0006oK-07 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:55:59 -0400 Received: by mail-qg0-f48.google.com with SMTP id i50so1185610qgf.21 for ; Tue, 21 Oct 2014 09:55:58 -0700 (PDT) X-Received: by 10.229.37.138 with SMTP id x10mr32428243qcd.5.1413910558396; Tue, 21 Oct 2014 09:55:58 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.55.57 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:55:57 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:19 -0500 Message-Id: <1413910544-20150-8-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.48 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler This patch extends arm_excp_unmasked() according to ARM ARMv7 and ARM ARMv8 (all EL running in AArch32) and adds comments. If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Globally change Aarch# to AArch# - Fixed comment termination v4 -> v5 - Merge with v4 patch 10 Signed-off-by: Greg Bellows --- target-arm/cpu.h | 117 ++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 107 insertions(+), 10 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cb6ec5c..1a564b9 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1246,11 +1246,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) { CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_el(env); - unsigned int target_el = arm_excp_target_el(cs, excp_idx); - /* FIXME: Use actual secure state. */ - bool secure = false; - /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */ - bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; + bool secure = arm_is_secure(env); + /* ARMv7-M interrupt return works by loading a magic value * into the PC. On real hardware the load causes the * return to occur. The qemu implementation performs the @@ -1265,19 +1262,119 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) && (!IS_M(env) || env->regs[15] < 0xfffffff0); /* Don't take exceptions if they target a lower EL. */ - if (cur_el > target_el) { + if (cur_el > arm_excp_target_el(cs, excp_idx)) { return false; } + /* ARM ARMv7 B1.8.6 Asynchronous exception masking (table B1-12/B1-13) + * ARM ARMv8 G1.11.3 Asynchronous exception masking controls + * (table G1-18/G1-19) + */ switch (excp_idx) { case EXCP_FIQ: - if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) { - return true; + if (arm_feature(env, ARM_FEATURE_EL3) && arm_el_is_aa64(env, 3)) { + /* If EL3 is using AArch64 and FIQs are routed to EL3 masking is + * ignored in all exception levels except EL3. + */ + if ((env->cp15.scr_el3 & SCR_FIQ) && cur_el < 3) { + return true; + } + /* If we are in EL3 but FIQs are not routed to EL3 the exception + * is not taken but remains pending. + */ + if (!(env->cp15.scr_el3 & SCR_FIQ) && cur_el == 3) { + return false; + } + } + if (!secure) { + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (env->cp15.hcr_el2 & HCR_FMO) { + /* CPSR.F/PSTATE.F ignored if + * - exception is taken from Non-secure state + * - HCR.FMO == 1 + * - either: - not in Hyp mode + * - SCR.FIQ routes exception to monitor mode + * (EL3 in AArch32) + */ + if (cur_el < 2) { + return true; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.scr_el3 & SCR_FIQ) && + !arm_el_is_aa64(env, 3)) { + return true; + } + } else if (arm_el_is_aa64(env, 3) && + (env->cp15.scr_el3 & SCR_RW) && + cur_el == 2) { + /* FIQs not routed to EL2 but currently in EL2 (A64). + * Exception is not taken but remains pending. */ + return false; + } + } + /* In ARMv7 only applies if both Security Extensions (EL3) and + * Hypervirtualization Extensions (EL2) implemented, while + * for ARMv8 it applies also if only EL3 implemented. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && + (arm_feature(env, ARM_FEATURE_EL2) || + arm_feature(env, ARM_FEATURE_V8))) { + /* CPSR.F/PSTATE.F ignored if + * - exception is taken from Non-secure state + * - SCR.FIQ routes exception to monitor mode + * - SCR.FW bit is set to 0 + * - HCR.FMO == 0 (if EL2 implemented) + */ + if ((env->cp15.scr_el3 & SCR_FIQ) && + !(env->cp15.scr_el3 & SCR_FW)) { + if (!arm_feature(env, ARM_FEATURE_EL2)) { + return true; + } else if (!(env->cp15.hcr_el2 & HCR_FMO)) { + return true; + } + } + } } return !(env->daif & PSTATE_F); case EXCP_IRQ: - if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { - return true; + if (arm_feature(env, ARM_FEATURE_EL3) && arm_el_is_aa64(env, 3)) { + /* If EL3 is using AArch64 and IRQs are routed to EL3 masking is + * ignored in all exception levels except EL3. + */ + if ((env->cp15.scr_el3 & SCR_IRQ) && cur_el < 3) { + return true; + } + /* If we are in EL3 but IRQ s are not routed to EL3 the exception + * is not taken but remains pending. + */ + if (!(env->cp15.scr_el3 & SCR_IRQ) && cur_el == 3) { + return false; + } + } + if (!secure) { + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (env->cp15.hcr_el2 & HCR_IMO) { + /* CPSR.I/PSTATE.I ignored if + * - exception is taken from Non-secure state + * - HCR.IMO == 1 + * - either: - not in Hyp mode + * - SCR.IRQ routes exception to monitor mode + * (EL3 in AArch32) + */ + if (cur_el < 2) { + return true; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.scr_el3 & SCR_IRQ) && + !arm_el_is_aa64(env, 3)) { + return true; + } + } else if (arm_el_is_aa64(env, 3) && + (env->cp15.scr_el3 & SCR_RW) && + cur_el == 2) { + /* IRQs not routed to EL2 but currently in EL2 (A64). + * Exception is not taken but remains pending. */ + return false; + } + } } return irq_unmasked; case EXCP_VFIQ: