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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id e89si23607408qga.40.2014.10.21.10.19.53 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:19:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgd68-0002PR-JX for patch@linaro.org; Tue, 21 Oct 2014 13:19:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42328) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjT-0007EV-Vh for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjP-000733-3k for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:27 -0400 Received: from mail-qg0-f47.google.com ([209.85.192.47]:37600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjP-00072v-0j for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:23 -0400 Received: by mail-qg0-f47.google.com with SMTP id i50so1130376qgf.20 for ; Tue, 21 Oct 2014 09:56:19 -0700 (PDT) X-Received: by 10.140.104.200 with SMTP id a66mr31605693qgf.37.1413910579633; Tue, 21 Oct 2014 09:56:19 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.18 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:18 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:43 -0500 Message-Id: <1413910544-20150-32-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.47 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 31/32] target-arm: make MAIR0/1 banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Signed-off-by: Greg Bellows ========== v5 -> v6 - Changed _el field variants to be array based Signed-off-by: Greg Bellows --- target-arm/cpu.h | 12 +++++++++++- target-arm/helper.c | 8 +++++--- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 82fc018..ebc2931 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -305,7 +305,17 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ - uint64_t mair_el1; + union { /* Memory attribute redirection */ + struct { + uint64_t _unused_mair_0; + uint32_t mair0_ns; + uint32_t mair1_ns; + uint64_t _unused_mair_1; + uint32_t mair0_s; + uint32_t mair1_s; + }; + uint64_t mair_el[4]; + }; union { /* vector base address register */ struct { uint64_t _unused_vbar; diff --git a/target-arm/helper.c b/target-arm/helper.c index f8e2eed..9cbea28 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -952,7 +952,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue = 0 }, /* For non-long-descriptor page tables these are PRRR and NMRR; * regardless they still act as reads-as-written for QEMU. @@ -961,11 +961,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), + offsetof(CPUARMState, cp15.mair0_ns) }, .resetfn = arm_cp_reset_ignore }, { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), + offsetof(CPUARMState, cp15.mair1_ns) }, .resetfn = arm_cp_reset_ignore }, { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,