From patchwork Tue Oct 21 16:55:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 39195 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id BB66D2039B for ; Tue, 21 Oct 2014 17:18:43 +0000 (UTC) Received: by mail-wi0-f198.google.com with SMTP id hi2sf1212656wib.5 for ; Tue, 21 Oct 2014 10:18:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=OBl9RA/l71HZAWRG+De1pzzWI9zuKtxXvkISgmlgpGA=; b=guZ2y/Z8AmsLnJo5zUzGm5UHNKXirtasGLxvPkcJol3mQ7jbd5D12Z/1mY/clJOJj4 FMzJzcVHkVKHiHOvgtdy3uI/ychxF6AaI+5PuxpIWRAs2JezBXW+R1T0fOlUz4p9SWYu Jt2hCIIX4g3zn8n4Azd79oeyfEhoiss7kIJZM8xHFFT5Hj9BeDW/kD5W+GA0Ne9ZlVg7 cR02LPKiSBfgzK2KyZMzXPzoTSsbQWJSjDzyJxWUyaZaOtsrlbEz0daRAslEIG7hbdUh pdIjG0a8A3O9eIp3wc1KrxQDnBvRLU6hOeHt/O+bMWa6SyegI6AAN/5aOp0yE4t1ImhO EWVw== X-Gm-Message-State: ALoCoQm2SN6wsR3jWA8nRmgV6RpVewKKj73v1wnIlZJzo0MdG2lS8XOQJQu5m8EEyDzJMbyAmuEk X-Received: by 10.112.99.72 with SMTP id eo8mr1986904lbb.7.1413911922674; Tue, 21 Oct 2014 10:18:42 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.23.133 with SMTP id m5ls81611laf.102.gmail; Tue, 21 Oct 2014 10:18:42 -0700 (PDT) X-Received: by 10.152.204.76 with SMTP id kw12mr35513672lac.37.1413911922511; Tue, 21 Oct 2014 10:18:42 -0700 (PDT) Received: from mail-la0-f48.google.com (mail-la0-f48.google.com. [209.85.215.48]) by mx.google.com with ESMTPS id k1si19927159lam.96.2014.10.21.10.18.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:18:42 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) client-ip=209.85.215.48; Received: by mail-la0-f48.google.com with SMTP id gi9so1428494lab.21 for ; Tue, 21 Oct 2014 10:18:42 -0700 (PDT) X-Received: by 10.153.8.164 with SMTP id dl4mr36287885lad.29.1413911922323; Tue, 21 Oct 2014 10:18:42 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.84.229 with SMTP id c5csp545065lbz; Tue, 21 Oct 2014 10:18:41 -0700 (PDT) X-Received: by 10.224.88.196 with SMTP id b4mr47680072qam.27.1413911920991; Tue, 21 Oct 2014 10:18:40 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id k2si4102154qad.18.2014.10.21.10.18.40 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:18:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:52616 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgd4x-0000dt-9c for patch@linaro.org; Tue, 21 Oct 2014 13:18:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjQ-00079q-TU for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjK-00070h-VI for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:24 -0400 Received: from mail-qa0-f53.google.com ([209.85.216.53]:62446) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjK-00070X-Qr for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:18 -0400 Received: by mail-qa0-f53.google.com with SMTP id v10so1156200qac.12 for ; Tue, 21 Oct 2014 09:56:18 -0700 (PDT) X-Received: by 10.140.90.20 with SMTP id w20mr44322928qgd.88.1413910578462; Tue, 21 Oct 2014 09:56:18 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.17 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:18 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:42 -0500 Message-Id: <1413910544-20150-31-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.53 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v6 -> v7 - Fix linux-user/arm/target-cpu.h to use array based tpidr_el. - Fix linux-user/main.c to use array based tpidrro_el. - Remove tab identified by checkpatch failure. - FIx linux-user/aarch64/target_cpu.h to use array based tpidr_el. v5 -> v6 - Changed _el field variants to be array based - Rework data layout for correct aliasing - Merged CONTEXTIDR and CONTEXTIDR_EL1 reginfo entries v3 -> v4 - Fix tpidrprw mapping Signed-off-by: Greg Bellows --- linux-user/aarch64/target_cpu.h | 2 +- linux-user/arm/target_cpu.h | 2 +- linux-user/main.c | 72 ++++++++++++++++++++--------------------- target-arm/cpu.h | 35 +++++++++++++++++--- target-arm/helper.c | 37 ++++++++++++--------- target-arm/op_helper.c | 2 +- 6 files changed, 91 insertions(+), 59 deletions(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h index 21560ef..b5593dc 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user/aarch64/target_cpu.h @@ -32,7 +32,7 @@ static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is * different from AArch32 Linux, which uses TPIDRRO. */ - env->cp15.tpidr_el0 = newtls; + env->cp15.tpidr_el[0] = newtls; } #endif diff --git a/linux-user/arm/target_cpu.h b/linux-user/arm/target_cpu.h index 39d65b6..d8a534d 100644 --- a/linux-user/arm/target_cpu.h +++ b/linux-user/arm/target_cpu.h @@ -29,7 +29,7 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) { - env->cp15.tpidrro_el0 = newtls; + env->cp15.tpidrro_el[0] = newtls; } #endif diff --git a/linux-user/main.c b/linux-user/main.c index 483eb3f..4f2bae2 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -564,7 +564,7 @@ do_kernel_trap(CPUARMState *env) end_exclusive(); break; case 0xffff0fe0: /* __kernel_get_tls */ - env->regs[0] = env->cp15.tpidrro_el0; + env->regs[0] = env->cp15.tpidrro_el[0]; break; case 0xffff0f60: /* __kernel_cmpxchg64 */ arm_kernel_cmpxchg64_helper(env); @@ -2804,7 +2804,7 @@ void cpu_loop(CPUCRISState *env) CPUState *cs = CPU(cris_env_get_cpu(env)); int trapnr, ret; target_siginfo_t info; - + while (1) { trapnr = cpu_cris_exec (env); switch (trapnr) { @@ -2822,13 +2822,13 @@ void cpu_loop(CPUCRISState *env) /* just indicate that signals should be handled asap */ break; case EXCP_BREAK: - ret = do_syscall(env, - env->regs[9], - env->regs[10], - env->regs[11], - env->regs[12], - env->regs[13], - env->pregs[7], + ret = do_syscall(env, + env->regs[9], + env->regs[10], + env->regs[11], + env->regs[12], + env->regs[13], + env->pregs[7], env->pregs[11], 0, 0); env->regs[10] = ret; @@ -2863,7 +2863,7 @@ void cpu_loop(CPUMBState *env) CPUState *cs = CPU(mb_env_get_cpu(env)); int trapnr, ret; target_siginfo_t info; - + while (1) { trapnr = cpu_mb_exec (env); switch (trapnr) { @@ -2884,13 +2884,13 @@ void cpu_loop(CPUMBState *env) /* Return address is 4 bytes after the call. */ env->regs[14] += 4; env->sregs[SR_PC] = env->regs[14]; - ret = do_syscall(env, - env->regs[12], - env->regs[5], - env->regs[6], - env->regs[7], - env->regs[8], - env->regs[9], + ret = do_syscall(env, + env->regs[12], + env->regs[5], + env->regs[6], + env->regs[7], + env->regs[8], + env->regs[9], env->regs[10], 0, 0); env->regs[3] = ret; @@ -3424,7 +3424,7 @@ void stop_all_tasks(void) void init_task_state(TaskState *ts) { int i; - + ts->used = 1; ts->first_free = ts->sigqueue_table; for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { @@ -4271,23 +4271,23 @@ int main(int argc, char **argv, char **envp) env->regs[12] = regs->r12; env->regs[13] = regs->r13; env->regs[14] = regs->r14; - env->regs[15] = regs->r15; - env->regs[16] = regs->r16; - env->regs[17] = regs->r17; - env->regs[18] = regs->r18; - env->regs[19] = regs->r19; - env->regs[20] = regs->r20; - env->regs[21] = regs->r21; - env->regs[22] = regs->r22; - env->regs[23] = regs->r23; - env->regs[24] = regs->r24; - env->regs[25] = regs->r25; - env->regs[26] = regs->r26; - env->regs[27] = regs->r27; - env->regs[28] = regs->r28; - env->regs[29] = regs->r29; - env->regs[30] = regs->r30; - env->regs[31] = regs->r31; + env->regs[15] = regs->r15; + env->regs[16] = regs->r16; + env->regs[17] = regs->r17; + env->regs[18] = regs->r18; + env->regs[19] = regs->r19; + env->regs[20] = regs->r20; + env->regs[21] = regs->r21; + env->regs[22] = regs->r22; + env->regs[23] = regs->r23; + env->regs[24] = regs->r24; + env->regs[25] = regs->r25; + env->regs[26] = regs->r26; + env->regs[27] = regs->r27; + env->regs[28] = regs->r28; + env->regs[29] = regs->r29; + env->regs[30] = regs->r30; + env->regs[31] = regs->r31; env->sregs[SR_PC] = regs->pc; } #elif defined(TARGET_MIPS) @@ -4349,7 +4349,7 @@ int main(int argc, char **argv, char **envp) env->regs[12] = regs->r12; env->regs[13] = regs->r13; env->regs[14] = info->start_stack; - env->regs[15] = regs->acr; + env->regs[15] = regs->acr; env->pc = regs->erp; } #elif defined(TARGET_S390X) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e018f74..82fc018 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -316,11 +316,36 @@ typedef struct CPUARMState { uint64_t vbar_el[4]; }; uint64_t mvbar; /* (monitor) vector base address register */ - uint32_t c13_fcse; /* FCSE PID. */ - uint64_t contextidr_el1; /* Context ID. */ - uint64_t tpidr_el0; /* User RW Thread register. */ - uint64_t tpidrro_el0; /* User RO Thread register. */ - uint64_t tpidr_el1; /* Privileged Thread register. */ + struct { /* FCSE PID. */ + uint32_t fcseidr_ns; + uint32_t fcseidr_s; + }; + union { /* Context ID. */ + struct { + uint64_t _unused_contextidr; + uint64_t contextidr_ns; + uint64_t contextidr_s; + }; + uint64_t contextidr_el[2]; + }; + union { /* User RW Thread register. */ + struct { + uint64_t tpidrurw_ns; + uint64_t tpidrprw_ns; + uint64_t htpidr; + uint64_t _tpidr_el3; + }; + uint64_t tpidr_el[4]; + }; + /* The secure banks of these registers don't map anywhere */ + uint64_t tpidrurw_s; + uint64_t tpidrprw_s; + uint64_t tpidruro_s; + + union { /* User RO Thread register. */ + uint64_t tpidruro_ns; + uint64_t tpidrro_el[1]; + }; uint64_t c14_cntfrq; /* Counter Frequency register */ uint64_t c14_cntkctl; /* Timer Control register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; diff --git a/target-arm/helper.c b/target-arm/helper.c index 8b0a327..f8e2eed 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -420,12 +420,15 @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo cp_reginfo[] = { { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), + .access = PL1_RW, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.fcseidr_s), + offsetof(CPUARMState, cp15.fcseidr_ns) }, .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, + .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.contextidr_s), + offsetof(CPUARMState, cp15.contextidr_ns) }, .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, REGINFO_SENTINEL }; @@ -1038,23 +1041,27 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, .access = PL0_RW, - .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 }, + .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, - .access = PL0_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), - .resetfn = arm_cp_reset_ignore }, + .access = PL0_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) } }, { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, - .access = PL0_R|PL1_W, - .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 }, + .access = PL0_R|PL1_W, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]) }, { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, - .access = PL0_R|PL1_W, - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), - .resetfn = arm_cp_reset_ignore }, - { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, + .access = PL0_R|PL1_W, .resetvalue = 0, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), + offsetoflow32(CPUARMState, cp15.tpidruro_ns) } }, + { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 }, + .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, + { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), + offsetoflow32(CPUARMState, cp15.tpidrprw_ns) } }, REGINFO_SENTINEL }; @@ -5103,7 +5110,7 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, /* Fast Context Switch Extension. */ if (address < 0x02000000) - address += env->cp15.c13_fcse; + address += A32_BANKED_CURRENT_REG_GET(env, fcseidr); if ((sctlr & SCTLR_M) == 0) { /* MMU/MPU disabled. */ diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index a8dea5a..2bed914 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -575,7 +575,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) * short descriptor format (in which case it holds both PROCID and ASID), * since we don't implement the optional v7 context ID masking. */ - contextidr = extract64(env->cp15.contextidr_el1, 0, 32); + contextidr = extract64(env->cp15.contextidr_el[1], 0, 32); switch (bt) { case 3: /* linked context ID match */