From patchwork Tue Oct 21 16:55:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 39189 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f69.google.com (mail-ee0-f69.google.com [74.125.83.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0EA642039B for ; Tue, 21 Oct 2014 17:13:34 +0000 (UTC) Received: by mail-ee0-f69.google.com with SMTP id b57sf674594eek.8 for ; Tue, 21 Oct 2014 10:13:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:date :message-id:in-reply-to:references:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :errors-to:sender:x-original-sender :x-original-authentication-results:mailing-list; bh=MxjTAUdS8+qo7nd7KEkDCeNxDPkdkNcXnI6W1mJVtNs=; b=JUO12vPa6sEm3b3hMk3opvv9ET+vUvQkFVyzxqhyyHGM8pIboptFzN+Y/0+n3DDIZv 0sJOAACleqknUt4EU6DvuGvy0Xn6KF1aXfVJbTg+djpd6bHkL703ojLD9x0h3z+X85dC ZjE+szk4p97x7G1tj9KMIUdJxgvj60KQtUS354eISdzNyRaujxu7BNc4yhMrmYb9HV+E qPSqtn0CowNhuQejS2c9lXLblbIeA7v5NDro3OzqPDlp6bOlNxKmeAVfzT1G89OQa84W lbPUkGyQFnawIcattg5m9Ph240JzYqT5o5Z8ERBQIHoa85Y7cq0Bl4FCW03U/W7Li2de z8cw== X-Gm-Message-State: ALoCoQn22AD8mlR420CfrDx6Gm5qu6dC8ijpglkmgxwW2Hp9NZfTZfrv/Z8c83TW1FRf9X4izEpO X-Received: by 10.180.83.134 with SMTP id q6mr3786643wiy.7.1413911614187; Tue, 21 Oct 2014 10:13:34 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.205.108 with SMTP id lf12ls72439lac.48.gmail; Tue, 21 Oct 2014 10:13:33 -0700 (PDT) X-Received: by 10.112.247.43 with SMTP id yb11mr36314680lbc.51.1413911613782; Tue, 21 Oct 2014 10:13:33 -0700 (PDT) Received: from mail-la0-f48.google.com (mail-la0-f48.google.com. [209.85.215.48]) by mx.google.com with ESMTPS id ww1si19876220lbb.128.2014.10.21.10.13.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:13:33 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) client-ip=209.85.215.48; Received: by mail-la0-f48.google.com with SMTP id gi9so1420403lab.21 for ; Tue, 21 Oct 2014 10:13:33 -0700 (PDT) X-Received: by 10.112.97.135 with SMTP id ea7mr36482606lbb.46.1413911613616; Tue, 21 Oct 2014 10:13:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.84.229 with SMTP id c5csp543948lbz; Tue, 21 Oct 2014 10:13:32 -0700 (PDT) X-Received: by 10.140.82.144 with SMTP id h16mr43908681qgd.40.1413911612134; Tue, 21 Oct 2014 10:13:32 -0700 (PDT) Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g3si23510108qag.72.2014.10.21.10.13.31 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:13:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52554 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgczx-0000wv-5u for patch@linaro.org; Tue, 21 Oct 2014 13:13:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42199) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjL-00071S-1S for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjF-0006xQ-Q4 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:18 -0400 Received: from mail-qc0-f175.google.com ([209.85.216.175]:52138) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjF-0006xF-Ls for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:13 -0400 Received: by mail-qc0-f175.google.com with SMTP id b13so1428882qcw.6 for ; Tue, 21 Oct 2014 09:56:13 -0700 (PDT) X-Received: by 10.224.23.67 with SMTP id q3mr22335156qab.92.1413910573229; Tue, 21 Oct 2014 09:56:13 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.12 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:12 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:36 -0500 Message-Id: <1413910544-20150-25-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.175 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 24/32] target-arm: make c2_mask and c2_base_mask banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This avoids recalculating them on switches from secure to non-secure world. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Switch to use distinct CPREG secure flags v4 -> v5 - Changed c2_mask updates to use the TTBCR cpreg bank flag for selcting the secure bank instead of the A32_BANKED_CURRENT macro. This more accurately chooses the correct bank matching that of the TTBCR being accessed. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 ++++++++-- target-arm/helper.c | 24 ++++++++++++++++++------ 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 76c4ef8..785eab3 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -226,8 +226,14 @@ typedef struct CPUARMState { }; uint64_t tcr_el[4]; }; - uint32_t c2_mask; /* MMU translation table base selection mask. */ - uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ + struct { /* MMU translation table base selection mask. */ + uint32_t c2_mask_ns; + uint32_t c2_mask_s; + }; + struct { /* MMU translation table base 0 mask. */ + uint32_t c2_base_mask_ns; + uint32_t c2_base_mask_s; + }; uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ uint32_t c3; /* MMU domain access control register diff --git a/target-arm/helper.c b/target-arm/helper.c index caab8ce..046d81c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1597,8 +1597,14 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, * and the c2_mask and c2_base_mask values are meaningless. */ raw_write(env, ri, value); - env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); - env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); + + /* Update the masks corresponding to the the TTBCR bank being written */ + A32_BANKED_REG_SET(env, c2_mask, + ARM_CP_SECSTATE_TEST(ri, ARM_CP_SECSTATE_S), + ~(((uint32_t)0xffffffffu) >> maskshift)); + A32_BANKED_REG_SET(env, c2_base_mask, + ARM_CP_SECSTATE_TEST(ri, ARM_CP_SECSTATE_S), + ~((uint32_t)0x3fffu >> maskshift)); } static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1617,9 +1623,15 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - env->cp15.c2_base_mask = 0xffffc000u; + /* Rest both the TTBCR as well as the masks corresponding to the bank of + * the TTBCR being reset. + */ + A32_BANKED_REG_SET(env, c2_base_mask, + ARM_CP_SECSTATE_TEST(ri, ARM_CP_SECSTATE_S), + 0xffffc000u); + A32_BANKED_REG_SET(env, c2_mask, + ARM_CP_SECSTATE_TEST(ri, ARM_CP_SECSTATE_S), 0); raw_write(env, ri, 0); - env->cp15.c2_mask = 0; } static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4498,7 +4510,7 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table, * AArch32 there is a secure and non-secure instance of the translation * table registers. */ - if (address & env->cp15.c2_mask) { + if (address & A32_BANKED_CURRENT_REG_GET(env, c2_mask)) { if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) { /* Translation table walk disabled for TTBR1 */ return false; @@ -4510,7 +4522,7 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table, return false; } *table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & - env->cp15.c2_base_mask; + A32_BANKED_CURRENT_REG_GET(env, c2_base_mask); } *table |= (address >> 18) & 0x3ffc; return true;