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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id bp5si15501359wjb.86.2014.10.21.10.06.59 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:06:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgctc-0006PS-WF for patch@linaro.org; Tue, 21 Oct 2014 13:06:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjG-0006rW-85 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjB-0006uy-Fc for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:14 -0400 Received: from mail-qc0-f179.google.com ([209.85.216.179]:53605) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjB-0006un-Cw for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:09 -0400 Received: by mail-qc0-f179.google.com with SMTP id x3so1260508qcv.38 for ; Tue, 21 Oct 2014 09:56:09 -0700 (PDT) X-Received: by 10.229.106.68 with SMTP id w4mr47621158qco.18.1413910568948; Tue, 21 Oct 2014 09:56:08 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.08 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:08 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:31 -0500 Message-Id: <1413910544-20150-20-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.179 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2202465..bd6c5b2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -211,6 +211,7 @@ typedef struct CPUARMState { uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; uint64_t vbar_el[4]; /* vector base address register */ + uint64_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index af62074..9929c27 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2416,6 +2416,9 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = { .access = PL3_RW | PL1_R, .resetvalue = 0, .writefn = nsacr_write, .readfn = nsacr_read, .fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) }, + { .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, REGINFO_SENTINEL }; @@ -4364,16 +4367,16 @@ void arm_cpu_do_interrupt(CPUState *cs) cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } - /* High vectors. */ - if (env->cp15.c1_sys & SCTLR_V) { - /* when enabled, base address cannot be remapped. */ + + if (new_mode == ARM_CPU_MODE_MON) { + addr += env->cp15.mvbar; + } else if (env->cp15.c1_sys & SCTLR_V) { + /* High vectors. When enabled, base address cannot be remapped. */ addr += 0xffff0000; } else { /* ARM v7 architectures provide a vector base address register to remap * the interrupt vector table. - * This register is only followed in non-monitor mode, and has a secure - * and un-secure copy. Since the cpu is always in a un-secure operation - * and is never in monitor mode this feature is always active. + * This register is only followed in non-monitor mode, and is banked. * Note: only bits 31:5 are valid. */ addr += env->cp15.vbar_el[1];