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[208.118.235.17]) by mx.google.com with ESMTPS id a8si23439918qas.71.2014.10.21.10.00.38 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:00:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Received: from localhost ([::1]:52435 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcnW-0004tq-MU for patch@linaro.org; Tue, 21 Oct 2014 13:00:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41944) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj5-0006eo-Iy for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgciz-0006ng-MZ for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:03 -0400 Received: from mail-qc0-f176.google.com ([209.85.216.176]:51372) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgciz-0006nU-JI for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:55:57 -0400 Received: by mail-qc0-f176.google.com with SMTP id r5so1239980qcx.35 for ; Tue, 21 Oct 2014 09:55:55 -0700 (PDT) X-Received: by 10.140.81.210 with SMTP id f76mr44881753qgd.60.1413910553058; Tue, 21 Oct 2014 09:55:53 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.55.52 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:55:52 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:13 -0500 Message-Id: <1413910544-20150-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.176 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 01/32] target-arm: increase arrays of registers R13 & R14 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank index 7). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell ========== v5 -> v6 - Updated vmstate_arm_cpu versioning from 20 to 21 Signed-off-by: Greg Bellows --- target-arm/cpu.h | 4 ++-- target-arm/machine.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 690686c..e0e3f9b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -153,8 +153,8 @@ typedef struct CPUARMState { /* Banked registers. */ uint64_t banked_spsr[8]; - uint32_t banked_r13[6]; - uint32_t banked_r14[6]; + uint32_t banked_r13[8]; + uint32_t banked_r14[8]; /* These hold r8-r12. */ uint32_t usr_regs[5]; diff --git a/target-arm/machine.c b/target-arm/machine.c index 5776ee0..6437690 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -238,8 +238,8 @@ const VMStateDescription vmstate_arm_cpu = { }, VMSTATE_UINT32(env.spsr, ARMCPU), VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), - VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), + VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), + VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),