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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id iy2si8643938vdb.3.2014.10.21.10.07.00 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:07:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52485 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgctd-0006Pd-Mr for patch@linaro.org; Tue, 21 Oct 2014 13:06:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42073) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjC-0006mS-HG for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj7-0006rv-0j for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:10 -0400 Received: from mail-qg0-f51.google.com ([209.85.192.51]:63322) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj6-0006ro-TI for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:04 -0400 Received: by mail-qg0-f51.google.com with SMTP id z107so1200350qgd.10 for ; Tue, 21 Oct 2014 09:56:04 -0700 (PDT) X-Received: by 10.224.40.70 with SMTP id j6mr29771678qae.21.1413910563964; Tue, 21 Oct 2014 09:56:03 -0700 (PDT) Received: from gbellows-linaro.qualcomm.com ([67.52.129.61]) by mx.google.com with ESMTPSA id a3sm11122116qaa.49.2014.10.21.09.56.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 09:56:03 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Date: Tue, 21 Oct 2014 11:55:25 -0500 Message-Id: <1413910544-20150-14-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.51 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v7 13/32] target-arm: insert AArch32 cpregs twice into hashtable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: greg.bellows@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.42 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Fabian Aggeler Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Fixed NS-bit number in the CPREG hash lookup from 27 to 29. - Switched to dedicated CPREG secure flags. - Fixed disablement of reset and migration of common 32/64-bit registers. - Globally replace Aarch# with AArch# v4 -> v5 - Added use of ARM CP secure/non-secure bank flags during register processing in define_one_arm_cp_reg_with_opaque(). We now only register the specified bank if only one flag is specified, otherwise we register both a secure and non-secure instance. Signed-off-by: Greg Bellows --- target-arm/helper.c | 90 ++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 75 insertions(+), 15 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5f3bdc0..37cd389 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3296,22 +3296,60 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, uint32_t *key = g_new(uint32_t, 1); ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; - if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { - /* The AArch32 view of a shared register sees the lower 32 bits - * of a 64 bit backing field. It is not migratable as the AArch64 - * view handles that. AArch64 also handles reset. - * We assume it is a cp15 register if the .cp field is left unset. - */ - if (r2->cp == 0) { - r2->cp = 15; + + if (state == ARM_CP_STATE_AA32) { + /* Clear the secure state flags and set based on incoming nsbit */ + r2->secure &= ~(ARM_CP_SECSTATE_S | ARM_CP_SECSTATE_NS); + r2->secure |= ARM_CP_SECSTATE_S << nsbit; + + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* Register is banked (using both entries in array). + * Overwriting fieldoffset as the array was only used to define + * banked registers but later only fieldoffset is used. + */ + r2->fieldoffset = r->bank_fieldoffsets[nsbit]; + + /* If V8 is enabled then we don't need to migrate or reset the + * AArch32 version of the banked registers as this will be handled + * through the AArch64 view. + * If v7 then we don't need to migrate or reset the AArch32 + * non-secure bank as this will be handled through the AArch64 + * view. In this case the secure bank is not mirrored, so we must + * preserve it's reset criteria and allow it to be migrated. + * + * The exception to the above is cpregs with a crn of 13 + * (specifically FCSEIDR and CONTEXTIDR) in which case there may + * not be an AArch64 equivalent for one or either bank so migration + * and reset must be preserved. + */ + if (r->state == ARM_CP_STATE_BOTH) { + if ((arm_feature(&cpu->env, ARM_FEATURE_V8) && r->crn != 13) || + nsbit) { + r2->type |= ARM_CP_NO_MIGRATE; + r2->resetfn = arm_cp_reset_ignore; + } + } + } else if (!nsbit) { + /* The register is not banked so we only want to allow migration of + * the non-secure instance. + */ + r2->type |= ARM_CP_NO_MIGRATE; + r2->resetfn = arm_cp_reset_ignore; } - r2->type |= ARM_CP_NO_MIGRATE; - r2->resetfn = arm_cp_reset_ignore; + + if (r->state == ARM_CP_STATE_BOTH) { + /* We assume it is a cp15 register if the .cp field is left unset. + */ + if (r2->cp == 0) { + r2->cp = 15; + } + #ifdef HOST_WORDS_BIGENDIAN - if (r2->fieldoffset) { - r2->fieldoffset += sizeof(uint32_t); - } + if (r2->fieldoffset) { + r2->fieldoffset += sizeof(uint32_t); + } #endif + } } if (state == ARM_CP_STATE_AA64) { /* To allow abbreviation of ARMCPRegInfo @@ -3476,8 +3514,30 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != state && r->state != ARM_CP_STATE_BOTH) { continue; } - add_cpreg_to_hashtable(cpu, r, opaque, state, - crm, opc1, opc2, SCR_NS); + if (state == ARM_CP_STATE_AA32) { + /* Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banked. + */ + uint32_t s = + r->secure & (ARM_CP_SECSTATE_S | ARM_CP_SECSTATE_NS); + if (ARM_CP_SECSTATE_S == s) { + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, !SCR_NS); + } else if (ARM_CP_SECSTATE_NS == s) { + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, SCR_NS); + } else { + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, !SCR_NS); + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, SCR_NS); + } + } else { + /* AArch64 registers get mapped to non-secure instance + * of AArch32 */ + add_cpreg_to_hashtable(cpu, r, opaque, state, + crm, opc1, opc2, SCR_NS); + } } } }