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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id l30si23505857qge.70.2014.10.15.03.09.02 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 15 Oct 2014 03:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:43454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XeLVu-00062H-4t for patch@linaro.org; Wed, 15 Oct 2014 06:09:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XeLIX-0000oN-Lm for qemu-devel@nongnu.org; Wed, 15 Oct 2014 05:55:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XeLIT-0000nl-DW for qemu-devel@nongnu.org; Wed, 15 Oct 2014 05:55:13 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:63581) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XeLIT-0000nY-2Y for qemu-devel@nongnu.org; Wed, 15 Oct 2014 05:55:09 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 99E43299AE4CA; Wed, 15 Oct 2014 10:55:04 +0100 (IST) Received: from localhost.localdomain (192.168.14.85) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 15 Oct 2014 10:55:06 +0100 From: Leon Alrae To: Date: Wed, 15 Oct 2014 10:54:20 +0100 Message-ID: <1413366860-7833-29-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1413366860-7833-1-git-send-email-leon.alrae@imgtec.com> References: <1413366860-7833-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.85] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: Peter Maydell Subject: [Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Peter Maydell Remove the functions gen_load_ACX and gen_store_ACX, which appear to have been unused since they were first introduced many years ago. These functions were the only places using the cpu_ACX[] array of TCG globals, so remove that and its accompanying regnames_ACX[] as well. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Leon Alrae --- target-mips/translate.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c23cb94..446eb8a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1104,7 +1104,7 @@ enum { /* global register indices */ static TCGv_ptr cpu_env; static TCGv cpu_gpr[32], cpu_PC; -static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC]; +static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget, bcond; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -1195,10 +1195,6 @@ static const char * const regnames_LO[] = { "LO0", "LO1", "LO2", "LO3", }; -static const char * const regnames_ACX[] = { - "ACX0", "ACX1", "ACX2", "ACX3", -}; - static const char * const fregnames[] = { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", @@ -1241,17 +1237,6 @@ static inline void gen_store_gpr (TCGv t, int reg) tcg_gen_mov_tl(cpu_gpr[reg], t); } -/* Moves to/from ACX register. */ -static inline void gen_load_ACX (TCGv t, int reg) -{ - tcg_gen_mov_tl(t, cpu_ACX[reg]); -} - -static inline void gen_store_ACX (TCGv t, int reg) -{ - tcg_gen_mov_tl(cpu_ACX[reg], t); -} - /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr (int from, int to) { @@ -17716,9 +17701,6 @@ void mips_tcg_init(void) cpu_LO[i] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUMIPSState, active_tc.LO[i]), regnames_LO[i]); - cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUMIPSState, active_tc.ACX[i]), - regnames_ACX[i]); } cpu_dspctrl = tcg_global_mem_new(TCG_AREG0, offsetof(CPUMIPSState, active_tc.DSPControl),